C8051F351-GMR Silicon Laboratories Inc, C8051F351-GMR Datasheet - Page 232

• Manufacturer Part Number: C8051F351-GMR
• Description: IC 8051 MCU 8K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F351-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x24b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F350DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• For Use With: 336-1083 - DEV KIT FOR F350/351/352/353
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

•
•
C8051F350/1/2/3
D
Revision 0.4 to Revision 1.0
•
•
•
•
•
•
•
•
•
•
•
•
Revision 1.0 to Revision 1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
232
OCUMENT
Removed preliminary tag and updated various specifications.
Updated package labeling and added "Lead-free (RoHS Compliant)" in Table 1.1, “Product Selection
Guide,” on page 18.
ADC chapter: Added Table 5.5, Table 5.6, Table 5.7, Table 5.8, and Table 5.9 on pages 63–65.
Temperature Sensor chapter: Added Offset Error and Slope Error specifications to Table 8.1, “Temper-
ature Sensor Electrical Characteristics,” on page 77.
Reset Sources chapter: Table 14.1, “Reset Electrical Characteristics,” on page 120: Added V
Time and changed “V
Flash Memory chapter: Clarified descriptions of Flash security features.
Oscillators chapter: Clarified external crystal initialization steps and added a specific 32.768 kHz crys-
tal example.
Oscillators chapter: Clarified external capacitor example.
Port I/O chapter: Figure 18.3 and Figure 18.4, Crossbar Priority Decoder Tables: Changed
PnSKIP[7:0] to PnSKIP[0:7] to match the Port I/O order.
SMBus chapter: SFR Definition 19.1, SMB0CF register: Added a description of the behavior of Timer 3
in split mode if SMBTOE is set.
PCA chapter: Updated Watchdog timer timeout intervals in Table 23.3 on page 221.
C2 chapter: Removed references to “boundary scans.”
Clarified text in Table 2.1, “Absolute Maximum Ratings,” on page 29.
Updated Digital Supply Current values in Table 3.1, “Global DC Electrical Characteristics,” on page 30.
Removed sentence in Section “5.2. Calibrating the ADC’ on page 44 that indicated the AD0CALC bit is
cleared by clearing the AD0INT flag.
Updated Table 5.3, “ADC0 Electrical Characteristics,” on page 61.
- ADC input current
- Burnout Current Source values
- AV+ Supply Current values
Added second note to SFR Definition 5.3.
Updated Table 6.1, “IDAC Electrical Characteristics,” on page 72.
- IDAC0 Gain-error Temp Co.
- IDAC0 Power consumption values
Clarified usage of VREF– pin in text and figure in 7. ‘Voltage Reference” on page 73.
Updated Table 7.1, “Voltage Reference Electrical Characteristics,” on page 75.
- VREF output voltage max and min
- Power Specifications
Corrected pins used by Comparator0 output in Section “9.1. Comparator0 Inputs and Outputs’ on
page 83.
Updated Comparator Power Consumptions values in Table 9.1, “Comparator Electrical Characteris-
tics,” on page 85.
Corrected maximum SMBus speed in Section “19. SMBus’ on page 151.
Updated Table 19.4, “SMBus Status Decoding,” on page 167.
- Slave Transmitter (0101 0XX)
- Slave Receiver (0001 00X)
Fixed Equation 23.4.
Added last step to procedure described in Section “23.3.2. Watchdog Timer Usage’ on page 221.
Changed Note 2 in Table 23.3, “Watchdog Timer Timeout Intervals1,” on page 221.
Added Section “24. Revision Specific Behavior’ on page 227.
C
HANGE
DD
POR Threshold” to “V
L
IST
Rev. 1.1
DD
Monitor Threshold.”
DD
Ramp