C8051F351-GMR Silicon Laboratories Inc, C8051F351-GMR Datasheet - Page 51

• Manufacturer Part Number: C8051F351-GMR
• Description: IC 8051 MCU 8K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F351-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x24b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F350DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• For Use With: 336-1083 - DEV KIT FOR F350/351/352/353
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Bits 7–0: ADC0CLK: ADC0 Modulator Clock Divisor.
Note: The Modulator Sampling Rate is not the ADC Output Word Rate. See Section 5.1.4 for
Bits 7–3: Unused: Read = 00000b, Write = don’t care.
Bits 2–0: DECI[10:8]: ADC0 Decimation Ratio Register, Bits 10–8.
This SFR can only be modified when ADC0 is in IDLE mode.
SFR Definition 5.5. ADC0DECH: ADC0 Decimation Ratio Register High Byte
R/W
R/W
Bit7
Bit7
—
This register establishes the Modulator Clock (MDCLK), by dividing down the system clock
(SYSCLK). The input signal is sampled by the modulator at a frequency of MDCLK / 128.
For optimal performance, the divider should be chosen such that the modulator clock is
equal to 2.4576 MHz (modulator sampling rate = 19.2 kHz).
The system clock is divided according to the equation:
MDCLK = SYSCLK / (ADC0CLK + 1)
details.
This register contains the high bits of the 11-bit ADC Decimation Ratio. The decimation ratio
determines the output word rate of ADC0, based on the Modulator Clock (MDCLK). See the
ADC0DECL register description for more information.
SFR Definition 5.4. ADC0CLK: ADC0 Modulator Clock Divisor
R/W
R/W
Bit6
Bit6
—
R/W
R/W
Bit5
Bit5
—
R/W
R/W
Bit4
Bit4
—
ADC0CLK
Rev. 1.1
R/W
R/W
Bit3
Bit3
—
DECI10
R/W
R/W
Bit2
Bit2
C8051F350/1/2/3
DECI9
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
DECI8
R/W
R/W
Bit0
Bit0
0xF7
0x9B
00000000
Reset Value
Reset Value
00000111
51