EM250-BBRD-R Ember, EM250-BBRD-R Datasheet - Page 10

• Manufacturer Part Number: EM250-BBRD-R
• Description: EM250 BREAKOUT BOARD
• Manufacturer: Ember
• Type: Transceiver, 802.15.4r

Specifications of EM250-BBRD-R

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1024

EM250
2 Top-Level Functional Description
120-0082-000S
Figure 2 shows a detailed block diagram of the EM250.
The radio receiver is a low-IF, super-heterodyne receiver. It utilizes differential signal paths to minimize noise
interference, and its architecture has been chosen to optimize co-existence with other devices within the
2.4GHz band (namely, IEEE 802.11g and Bluetooth). After amplification and mixing, the signal is filtered and
combined prior to being sampled by an ADC.
The digital receiver implements a coherent demodulator to generate a chip stream for the hardware-based
MAC. In addition, the digital receiver contains the analog radio calibration routines and control of the gain
within the receiver path.
The radio transmitter utilizes an efficient architecture in which the data stream directly modulates the VCO.
An integrated PA boosts the output power. The calibration of the TX path as well as the output power is con-
trolled by digital logic. If the EM250 is to be used with an external PA, the TX_ACTIVE signal should be used to
control the timing of the external switching logic.
The integrated 4.8 GHz VCO and loop filter minimize off-chip circuitry. Only a 24MHz crystal with its loading
capacitors is required to properly establish the PLL reference signal.
The MAC interfaces the data memory to the RX and TX baseband modules. The MAC provides hardware-based
IEEE 802.15.4 packet-level filtering. It supplies an accurate symbol time base that minimizes the synchroniza-
tion effort of the software stack and meets the protocol timing requirements. In addition, it provides timer
and synchronization assistance for the IEEE 802.15.4 CSMA-CA algorithm.
RF_TX_ALT_P,N
VREG_OUT
OSC32A
OSC32B
nRESET
RF_P,N
BIAS_R
OSCA
OSCB
PA select
PA
Regulator
RC-OSC
HF OSC
LF OSC
Internal
POR
Bias
LNA
PA
SYNTH
Figure 2. EM250 Block Diagram
ADC
IF
Page 10
DAC
ADC
TX_ACTIVE
GPIO multiplexor swtich
Baseband
PacketTrace
General
purpose
registers
SPI/I2C
UART/
timers
GPIO
MAC
GPIO[16:0]
+
Always
powered
controller
Interrupt
Watchdog
SRAM
manager
Data
5kB
Chip
XAP2b CPU
accelerator
Encryption
Program
Sleep
timer
128kB
SIF
Flash
SIF_CLK
SIF_MISO
SIF_MOSI
nSIF_LOAD