EM250-BBRD-R Ember, EM250-BBRD-R Datasheet - Page 27

• Manufacturer Part Number: EM250-BBRD-R
• Description: EM250 BREAKOUT BOARD
• Manufacturer: Ember
• Type: Transceiver, 802.15.4r

Specifications of EM250-BBRD-R

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1024

5 Functional Description—Application Modules
5.1
GPIO
In Application Mode, access to privileged areas is blocked while access to application-specific modules such as
GPIO, Serial Controllers (SC1 and SC2), General Purpose Timers, ADC, and Event Manager are enabled.
The EM250 has 17 multi-purpose GPIO pins that can be configured in a variety of ways. All pins have the fol-
lowing programmable features:
The information flow between the GPIO pin and its source are controlled by separate GPIO Data registers. The
GPIO_INH
registers enable the output signals for the GPIO Pins. The
resistors while
and
To configure a GPIO as an open source output, the
bit should be enabled, and the
drain, the
GPIO_DIR
Instead of changing the entire contents to the
be applied. Writing to the
to 1, while data bits that are already 1 are maintained. Writing to the
ister changes individual register bits from 1 to 0, while data bits that are already 0 are maintained.
Note that the value read from
current pin state. To observe the pin state, the
All registers controlling the GPIO pin definitions are unaffected by power cycling the main core voltage
(VDD_CORE).
GPIO_OUTL
Selectable as input, output, or bi-directional.
Output can be totem-pole, used as open drain or open source output for wired-OR applications.
Can have internal pull-up or pull-down.
GPIO_OUT
and
register can be used for the data.
GPIO_INL
GPIO_PDH
control the output level.
register should be set to 0, the
Note (1) :
Note (2) :
GPIO_CFG
GPIO_PDH/L
registers report the input level of the GPIO pins. The
and
GPIO_PUH/L
GPIO_DIRSETH/L
GPIO_DIRH/L
GPIO_DIRCLRH/L
GPIO_SETH/L
GPIO_OUTH/L
GPIO_CLRH/L
GPIO_INH/L
GPIO_SETH/L
Figure 5. GPIO Control Logic
GPIO_PDL
GPIO_OUTH/L
GPIO_DIR
Pull-down resistor is always disabled for Alternate GPIO functions
VREF_OUT, PTI_EN and PTI_DATA.
Pull-up resistor is always disabled for Alternate GPIO functions ADC 0,
ADC1, ADC2, ADC3, VREF_OUT, PTI_EN and PTI_DATA.
registers enable pull-down resistors on the GPIO Pins. The
or
register can be used for the data. To configure a GPIO as an open
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GPIO_DIRSETH/L
,
GPIO_SETH/L
OUT/DIR
GPIO_INH/L
GPIO_OUT
Alternate
functions
GPIO
GPIO_PU
registers with one write access, a limited change can
GPIO_PUH
VDD_PADS
, and
registers should be read.
register should be set to 0, the
register changes individual register bits from 0
register bit should be enabled, and the
Note (1)
Note (2)
GPIO_CLRH/L
and
GPIO_CLRH/L
GPIO_PUL
GPIO[16:0]
GPIO_DIRH
registers may not reflect the
registers enable pull-up
or
GPIO_DIRCLRH/L
and
GPIO_PD
GPIO_DIRL
EM250
120-0082-000S
GPIO_OUTH
register
reg-