PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 155

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 11-14: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5
 2009-2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
TMR7GIE
R/W-0
Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
(1)
TMR7GIE: TMR7 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR12IE: TMR12 to PR12 Match Interrupt Enable bit
1 = Enables the TMR12 to PR12 match interrupt
0 = Disables the TMR12 to PR12 match interrupt
TMR10IE: TMR10 to PR10 Match Interrupt Enable bit
1 = Enables the TMR10 to PR10 match interrupt
0 = Disables the TMR10 to PR10 match interrupt
TMR8IE: TMR8 to PR8 Match Interrupt Enable bit
1 = Enables the TMR8 to PR8 match interrupt
0 = Disables the TMR8 to PR8 match interrupt
TMR7IE: TMR7 Overflow Interrupt Enable bit
1 = Enables the TMR7 overflow interrupt
0 = Disables the TMR7 overflow interrupt
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enables the TMR6 to PR6 match interrupt
0 = Disables the TMR6 to PR6 match interrupt
TMR5IE: TMR5 Overflow Interrupt Enable bit
1 = Enables the TMR5 overflow interrupt
0 = Disables the TMR5 overflow interrupt
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enables the TMR4 to PR4 match interrupt
0 = Disables the TMR4 to PR4 match interrupt
TMR12IE
R/W-0
(1)
W = Writable bit
‘1’ = Bit is set
TMR10IE
R/W-0
(1)
TMR8IE
R/W-0
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87K22 FAMILY
TMR7IE
(1)
R/W-0
(1)
(1)
(1)
TMR6IE
R/W-0
x = Bit is unknown
TMR5IE
R/W-0
DS39960D-page 155
TMR4IE
R/W-0
bit 0