PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 172

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

corresponding Data Direction and Output Latch registers
PIC18F87K22 FAMILY
12.3
PORTB is an eight-bit wide, bidirectional port. The
are TRISB and LATB. All pins on PORTB are digital only.
EXAMPLE 12-2:
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
TABLE 12-3:
DS39960D-page 172
RB0/INT0/FLT0
RB1/INT1
RB2/INT2/CTED1
Legend:
Note 1:
CLRF
CLRF
MOVLW
MOVWF
Pin Name
PORTB, TRISB and
LATB Registers
PORTB
LATB
0CFh
TRISB
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Extended Microcontroller mode.
PORTB FUNCTIONS
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Function
INITIALIZING PORTB
CTED1
INT0
FLT0
INT1
INT2
RB0
RB1
RB2
Setting
TRIS
0
1
1
x
0
1
1
0
1
1
x
I/O
O
O
O
I
I
I
I
I
I
I
I
Type
DIG
TTL
DIG
TTL
DIG
TTL
I/O
ST
ST
ST
ST
ST
LATB<0> data output.
PORTB<0> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 0 input.
Enhanced PWM Fault input for ECCPx.
LATB<1> data output.
PORTB<1> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 1 input.
LATB<2> data output.
PORTB<2> data input; weak pull-up when RBPU bit is cleared.
External Interrupt 2 input.
CTMU Edge 1 input.
Four of the PORTB pins (RB<7:4>) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur. Any RB<7:4>
pin configured as an output will be excluded from the
interrupt-on-change comparison.
Comparisons with the input pins (of RB<7:4>) are
made with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB<7:4> are ORed
together to generate the RB Port Change Interrupt with
Flag bit, RBIF (INTCON<0>).
This
power-managed modes. To clear the interrupt in the
Interrupt Service Routine:
a)
b)
c)
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after one T
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
The RB<3:2> pins are multiplexed as CTMU edge
inputs. RB5 has an additional function for Timer3 and
Timer1. It can be configured for Timer3 clock input or
Timer1 external clock gate input.
Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
Wait one instruction cycle (such as executing a
NOP instruction).
Clear flag bit, RBIF.
interrupt
 2009-2011 Microchip Technology Inc.
can
Description
wake
the
device
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delay.
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