PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 256

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
19.4.2
The PWM duty cycle is specified to use CCP4, as an
example, by writing to the CCPR4L register and to the
CCP4CON<5:4> bits. Up to 10-bit resolution is avail-
able. The CCPR4L contains the eight MSbs and the
CCP4CON<5:4> bits contain the two LSbs. This 10-bit
value is represented by CCPR4L:CCP4CON<5:4>.
The following equation is used to calculate the PWM
duty cycle in time:
EQUATION 19-2:
CCPR4L and CCP4CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR4H until after a match between PR2 and TMR2
occurs (that is, the period is complete). In PWM mode,
CCPR4H is a read-only register.
TABLE 19-6:
19.4.3
To configure the CCP module for PWM operation,
using CCP4 as an example:
1.
2.
TABLE 19-7:
DS39960D-page 256
INTCON
RCON
PIR4
PIE4
IPR4
TRISB
TRISC
TRISE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2/4/6/8.
Note 1:
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
PWM Duty Cycle = (CCPR4L:CCP4CON<5:4>) •
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR4L register and CCP4CON<5:4> bits.
Name
2:
PWM Frequency
Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22).
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
PWM DUTY CYCLE
SETUP FOR PWM OPERATION
CCP10IF
CCP10IE
CCP10IP
GIE/GIEH
TRISC7
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
REGISTERS ASSOCIATED WITH PWM AND TIMERS
TRISB7
TRISE7
IPEN
Bit 7
T
OSC
(1)
(1)
(1)
• (TMR2 Prescale Value)
PEIE/GIEL
CCP9IE
CCP9IP
SBOREN
CCP9IF
TRISC6
TRISB6
TRISE6
Bit 6
2.44 kHz
FFh
(1)
(1)
(1)
16
10
TMR0IE
CCP8IF
CCP8IE
CCP8IP
TRISC5
TRISB5
TRISE5
Bit 5
CM
9.77 kHz
FFh
10
4
CCP7IE
CCP7IP
CCP7IF
TRISB4
TRISC4
TRISE4
INT0IE
Bit 4
RI
39.06 kHz
The CCPR4H register and a two-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR4H and two-bit latch match TMR2,
concatenated with an internal two-bit Q clock or two
bits of the TMR2 prescaler, the CCP4 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is shown in
EQUATION 19-3:
3.
4.
5.
Note:
FFh
10
1
Make the CCP4 pin an output by clearing the
appropriate TRIS bit.
Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
Configure the CCP4 module for PWM operation.
CCP6IF
CCP6IE
CCP6IP
TRISC3
TRISB3
TRISE3
PWM Resolution (max)
RBIE
Bit 3
TO
If the PWM duty cycle value is longer than
the PWM period, the CCP4 pin will not be
cleared.
156.25 kHz
3Fh
1
8
 2009-2011 Microchip Technology Inc.
TMR0IF
CCP5IE
CCP5IP
CCP5IF
TRISB2
TRISC2
TRISE2
Bit 2
PD
Equation
312.50 kHz
=
1Fh
CCP4IF
CCP4IE
CCP4IP
TRISB1
TRISC1
TRISE1
19-3:
INT0IF
log
-----------------------------bits
1
7
Bit 1
POR
log


---------------
F
F
PWM
2  
OSC
416.67 kHz


CCP3IF
CCP3IE
CCP3IP
TRISC0
TRISB0
TRISE0
6.58
17h
RBIF
Bit 0
BOR
1