PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 281

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.0
21.1
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D Converters, etc. The MSSP
module can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit™ (I
The I
hardware:
• Master mode
• Multi-Master mode
• Slave mode with 5-bit and 7-bit address masking
All members of the PIC18F87K22 family have two
MSSP modules, designated as MSSP1 and MSSP2.
Each module operates independently of the other.
21.2
Each MSSP module has three associated control regis-
ters. These include a status register (SSPxSTAT) and
two control registers (SSPxCON1 and SSPxCON2). The
use of these registers and their individual configuration
bits differ significantly depending on whether the MSSP
module is operated in SPI or I
Additional details are provided under the individual
sections.
 2009-2011 Microchip Technology Inc.
- Full Master mode
- Slave mode (with general address call)
(with address masking for both 10-bit and 7-bit
addressing)
Note:
Note:
2
C interface supports the following modes in
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
Control Registers
module, it is very important to pay close
different operational aspects of the same
Throughout this section, generic refer-
ences to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names and module I/O
signals use the generic designator ‘x’ to
indicate the use of a numeral to distinguish
a particular module when required. Control
bit names are not individuated.
In devices with more than one MSSP
attention to SSPxCON register names.
SSP1CON1
module,
SSP2CON1 control the same features for
two different modules.
while
and
2
2
C mode.
C™)
SSP1CON2
SSP1CON1
control
and
PIC18F87K22 FAMILY
21.3
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes
communication, typically three pins are used:
• Serial Data Out (SDOx) – RC5/SDO1 or
• Serial Data In (SDIx) – RC4/SDI1/SDA1 or
• Serial Clock (SCKx) – RC3/SCK1/SCL1 or
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SSx) – RF7/AN5/SS1 or RD7/SS2
Figure 21-1
module when operating in SPI mode.
FIGURE 21-1:
Note:
Note:
RD4/PSP4/SDO2
RD5/PSP5/SDI2/SDA2
RD6/PSP6/SCK2/SCL2
SCKx
SDOx
SDIx
SSx
Only port I/O names are used in this diagram for the
sake of brevity. Refer to the text for a full list of
multiplexed functions.
SPI Mode
of
The SSPxBUF register cannot be used with
read-modify-write instructions, such as BCF,
COMF, etc.
To avoid lost data in Master mode, a read of
the SSPxBUF must be performed to clear the
Buffer Full (BF) detect bit (SSPSTAT<0>)
between each transmission.
shows the block diagram of the MSSP
SPI
Read
SSx Control
are
Select
SMP:CKE
Edge
bit 0
Select
Edge
MSSP BLOCK DIAGRAM
(SPI MODE)
Enable
TRIS bit
SSPxBUF reg
Data to TXx/RXx in SSPxSR
SSPxSR reg
2
supported.
Clock Select
SSPM<3:0>
4
2
DS39960D-page 281
(
Prescaler
4, 16, 64
TMR2 Output
Write
To
Clock
Shift
Data Bus
Internal
2
accomplish
T
OSC
)