HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 121

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
6
5
4
3
2 to 0
Bit Name
STS2
STS1
STS0
NESEL

Initial
Value
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W

Description
Standby Timer Select 2 to 0
These bits set the wait time from when the external clock
oscillator starts functioning until the clock is supplied, in
shifting from standby mode, subactive mode, or subsleep
mode, to active mode or sleep mode. During the wait
time, this LSI automatically selects the on-chip oscillator
clock as its system clock and counts the number of wait
states. Select a wait time of 6.5 ms (oscillation
stabilization time) or longer, depending on the operating
frequency. Table 6.1 shows the relationship between the
STS2 to STS0 values and the wait time.
When using an external clock, set the wait time to be
100 µs or longer.
These bits also set the wait states for external oscillation
stabilization when system clock is switched from the on-
chip oscillator clock to the external clock by user
software.
The relationship between Nwait (number of wait states for
oscillation stabilization) and Nstby (number of wait states
for recovering to the standby mode) is as follows.
Nstby ≤ Nwait ≤ 2 × Nstby
Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch clock
signal (φ
generates the oscillator clock (φ
sampling frequency of the oscillator clock when the watch
clock signal (φ
clear NESEL to 0.
0: Sampling rate is φ
1: Sampling rate is φ
Reserved
These bits are always read as 0.
W
) and the external clock pulse generator
W
) is sampled. When φ
OSC
OSC
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Section 6 Power-Down Modes
OSC
). This bit selects the
OSC
= 4 to 20 MHz,
REJ09B0216-0100