HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 221

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The timer Z has a 16-bit timer with two channels. Figures 13.1, 13.2, and 13.3 show the block
diagrams of entire timer Z, its channel 0, and its channel 1, respectively. For details on the timer Z
functions, refer to table 13.1.
13.1
• Capability to process up to eight inputs/outputs
• Eight general registers (GR): four registers for each channel
• Selection of five counter clock sources: four internal clocks (φ, φ/2, φ/4, and φ/8) and an
• Seven selectable operating modes
• High-speed access by the internal 16-bit bus
• Any initial timer output value can be set
• Output of the timer is disabled by external trigger
TIM08Z0A_000120030300
 Independently assignable output compare or input capture functions
external clock
 Output compare function
 Input capture function
 Synchronous operation
 PWM mode
 Reset synchronous PWM mode
 Complementary PWM mode
 Buffer operation
 16-bit TCNT and GR registers can be accessed in high speed by a 16-bit bus interface
Selection of 0 output, 1 output, or toggle output
Rising edge, falling edge, or both edges
Timer counters_0 and _1 (TCNT_0 and TCNT_1) can be written simultaneously.
Simultaneous clearing by compare match or input capture is possible.
Up to six-phase PWM output can be provided with desired duty ratio.
Three-phase PWM output for normal and counter phases
Three-phase PWM output for non-overlapped normal and counter phases
The A/D conversion start trigger can be set for PWM cycles.
The input capture register can be consisted of double buffers.
The output compare register can automatically be modified.
Features
Section 13 Timer Z
Rev. 1.00 Sep. 16, 2005 Page 191 of 490
Section 13 Timer Z
REJ09B0216-0100