HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 364

16BIT MCU FLASH 56K, SMD, LQFP64

HD64F36077GHV

Manufacturer Part Number
HD64F36077GHV
Description
16BIT MCU FLASH 56K, SMD, LQFP64
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F36077GHV

No. Of I/o's
47
Ram Memory Size
4KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
4.5V
Core Size
16bit
Program Memory Size
56KB
Oscillator Type
External Only
Controller Family/series
H8/300H
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F36077GHV
Manufacturer:
RENESAS
Quantity:
340
Part Number:
HD64F36077GHV
Manufacturer:
Renesas
Quantity:
200
Part Number:
HD64F36077GHV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 17 I
Rev. 1.00 Sep. 16, 2005 Page 334 of 490
REJ09B0216-0100
Bit
3
2
Bit Name
STOP
AL/OVE
2
C Bus Interface 2 (IIC2)
Initial
Value
0
0
R/W
R/W
R/W
Description
Stop Condition Detection Flag
[Setting conditions]
[Clearing condition]
Arbitration Lost Flag/Overrun Error Flag
This flag indicates that arbitration was lost in master
mode with the I
been received while RDRF = 1 with the clock
synchronous format.
When two or more master devices attempt to seize the
bus at nearly the same time, if the I
detects data differing from the data it sent, it sets AL to 1
to indicate that the bus has been taken by another
master.
[Setting conditions]
[Clearing condition]
In master mode, when a stop condition is detected
after frame transfer
In slave mode, when a stop condition is detected after
the following events:
 A general call is invoked
 A start condition is detected
 The first byte in the slave address matches the
When 0 is written in STOP after reading STOP = 1
If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
When the SDA pin outputs high in master mode while
a start condition is detected
When the final bit is received with the clock
synchronous format while RDRF = 1
When 0 is written in AL/OVE after reading AL/OVE=1
address set in the SAR
2
C bus format and that the final bit has
2
C bus interface

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