HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 9

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 1 Overview................................................................................................1
1.1
1.2
1.3
1.4
Section 2 CPU........................................................................................................9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Section 3 Exception Handling .............................................................................43
3.1
3.2
Features.................................................................................................................................. 1
Block Diagram ....................................................................................................................... 3
Pin Arrangement .................................................................................................................... 4
Pin Functions ......................................................................................................................... 5
Address Space and Memory Map ........................................................................................ 10
Register Configuration......................................................................................................... 11
2.2.1
2.2.2
2.2.3
Data Formats........................................................................................................................ 15
2.3.1
2.3.2
Instruction Set ...................................................................................................................... 18
2.4.1
2.4.2
Addressing Modes and Effective Address Calculation........................................................ 29
2.5.1
2.5.2
Basic Bus Cycle ................................................................................................................... 34
2.6.1
2.6.2
CPU States ........................................................................................................................... 36
Usage Notes ......................................................................................................................... 37
2.8.1
2.8.2
2.8.3
Exception Sources and Vector Address ............................................................................... 44
Register Descriptions ........................................................................................................... 46
3.2.1
3.2.2
3.2.3
General Registers.................................................................................................... 12
Program Counter (PC) ............................................................................................ 13
Condition-Code Register (CCR)............................................................................. 13
General Register Data Formats ............................................................................... 15
Memory Data Formats ............................................................................................ 17
Table of Instructions Classified by Function .......................................................... 18
Basic Instruction Formats ....................................................................................... 28
Addressing Modes .................................................................................................. 29
Effective Address Calculation ................................................................................ 32
Access to On-Chip Memory (RAM, ROM)............................................................ 34
On-Chip Peripheral Modules .................................................................................. 35
Notes on Data Access to Empty Areas ................................................................... 37
EEPMOV Instruction.............................................................................................. 37
Bit-Manipulation Instruction .................................................................................. 37
Interrupt Edge Select Register 1 (IEGR1) .............................................................. 46
Interrupt Edge Select Register 2 (IEGR2) .............................................................. 47
Interrupt Enable Register 1 (IENR1) ...................................................................... 48
Contents
Rev. 1.00 Sep. 16, 2005 Page ix of xxx