HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 370

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 17 I
17.4.3
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. For master receive mode operation timing, refer to
figures 17.7 and 17.8. The reception procedure and operations in master receive mode are shown
below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise
4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition.
7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.
8. The operation returns to the slave receive mode.
Rev. 1.00 Sep. 16, 2005 Page 340 of 490
REJ09B0216-0100
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF
is cleared to 0.
receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is
fixed low until ICDRR is read.
This enables the issuance of the stop condition after the next reception.
Master Receive Operation
2
C Bus Interface 2 (IIC2)