PN5120A0HN/C2,551 NXP Semiconductors, PN5120A0HN/C2,551 Datasheet - Page 30

• Manufacturer Part Number: PN5120A0HN/C2,551
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C2,551

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.1.14 BitFramingReg
Adjustments for bit oriented frames.
Table 42.
Table 43.
Bit
7
6 to 4
3
2 to 0
Access
Rights
StartSend
Symbol
StartSend
RxAlign
-
TxLastBits
BitFramingReg register (address 0Dh); reset value: 00h, 00000000b
Description of BitFramingReg bits
w
7
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
Description
Set to logic 1, the transmission of data starts.
This bit is only valid in combination with the Transceive command.
Used for reception of bit oriented frames: RxAlign defines the bit position
for the first bit received to be stored in the FIFO. Further received bits are
stored at the following bit positions.
Example:
RxAlign = 0: the LSB of the received bit is stored at bit 0, the second
RxAlign = 1: the LSB of the received bit is stored at bit 1, the second
RxAlign = 7: the LSB of the received bit is stored at bit 7, the second
This bit shall only be used for bitwise anticollision at 106 kbit/s in Passive
Communication mode. In all other modes it shall be set to logic 0.
Reserved for future use.
Used for transmission of bit oriented frames: TxLastBits defines the
number of bits of the last byte that shall be transmitted. A 000 indicates
that all bits of the last byte shall be transmitted.
r/w
6
111336
RxAlign
r/w
5
received bit is stored at bit position 1.
received bit is stored at bit position 2.
received bit is stored in the following byte at bit position 0.
r/w
4
RFU
3
0
r/w
2
Transmission module
TxLastBits
© NXP B.V. 2011. All rights reserved.
r/w
1
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r/w
0