PN5120A0HN/C2,551 NXP Semiconductors, PN5120A0HN/C2,551 Datasheet - Page 46

• Manufacturer Part Number: PN5120A0HN/C2,551
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C2,551

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.2.15 TypeBReg
9.2.2.16 SerialSpeedReg
Table 74.
Table 75.
Selects the speed of the serial UART interface.
Table 76.
Bit
7
6
5
4
3
2
1 to 0
Access
Rights
Access
Rights
Symbol
RxSOFReq
RxEOFReq
-
EOFSOFWidth If this bit is set to logic 1 and EOFSOFAdjust bit is logic 0, the SOF
NoTxSOF
NoTxEOF
TxEGT
RxSOF
TypeBReg register (address 1Eh); reset value: 00h, 00000000b
Description of TypeBReg bits
SerialSpeedReg register (address 1Fh); reset value: EBh, 11101011b
Req
r/w
r/w
7
7
All information provided in this document is subject to legal disclaimers.
RxEOF
BR_T0
Req
Rev. 3.6 — 10 March 2011
r/w
r/w
6
6
Description
If this bit is set to logic 1, the SOF is required. A datastream starting
without SOF is ignored.
If this bit is cleared, a datastream with and without SOF is accepted.
The SOF will be removed and not written into the FIFO.
If this bit is set to logic 1, the EOF is required. A datastream ending
without EOF will generate a Protocol-Error. If this bit is cleared, a
datastream with and without EOF is accepted. The EOF will be
removed and not written into the FIFO.
Reserved for future use.
and EOF will have the maximum length defined in ISO/IEC 14443B.
If this bit is cleared and EOFSOFAdjust bit is logic 0, the SOF and
EOF will have the minimum length defined in ISO/IEC 14443B.
If this bit is set to 1 and the EOFSOFadjust bit is logic 1 will result in
SOF low = (11etu − 8 cycles)/fc
SOF high = (2 etu + 8 cycles)/fc
EOF low = (11 etu − 8 cycles)/fc
If this bit is set to 0 and the EOFSOFAdjust bit is logic 1 will result in
an incorrect system behavior in respect to ISO specification.
If this bit is set to logic 1, the generation of the SOF is suppressed.
If this bit is set to logic 1, the generation of the EOF is suppressed.
These bits define the length of the EGT.
Value Description
00 0 bit
01 1 bit
10 2 bits
11 3 bits
111336
RFU
r/w
5
0
5
EOFSO
FWidth
r/w
r/w
4
4
NoTxSOF NoTxEOF
r/w
r/w
3
3
BR_T1
r/w
2
r/w
2
Transmission module
© NXP B.V. 2011. All rights reserved.
r/w
1
r/w
1
PN512
TxEGT
46 of 125
r/w
r/w
0
0