PN5120A0HN/C2,551 NXP Semiconductors, PN5120A0HN/C2,551 Datasheet - Page 33

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PN5120A0HN/C2,551

Manufacturer Part Number
PN5120A0HN/C2,551
Description
IC TRANSMISSION MOD 40-HVQFN
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PN5120A0HN/C2,551

Rf Type
Read / Write
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B
Package / Case
40-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Quantity
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Part Number:
PN5120A0HN/C2,551
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NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.2.2 ModeReg
Defines general mode settings for transmitting and receiving.
Table 48.
Table 49.
Bit
7
6
5
4
3
2
1 to 0
Access
Rights
MSBFirst Detect Sync TxWaitRF RxWaitRF PolSigin ModeDetOff
Symbol
MSBFirst
Detect Sync
TxWaitRF
RxWaitRF
PolSigin
ModeDetOff
CRCPreset
ModeReg register (address 11h); reset value: 3Bh, 00111011b
Description of ModeReg bits
r/w
7
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
r/w
6
Description
Set to logic 1, the CRC co-processor calculates the CRC with MSB
first and the CRCResultMSB and the CRCResultLSB in the
CRCResultReg register are bit reversed.
Note: During RF communication this bit is ignored.
If set to logic 1, the contactless UART waits for the value F0h before
the receiver is activated and F0h is added as a Sync-byte for
transmission.
This bit is only valid for 106 kbit during NFCIP-1 data exchange
protocol.
In all other modes it shall be set to logic 0.
Set to logic 1 the transmitter in reader/writer or initiator mode for
NFCIP-1 can only be started, if an RF field is generated.
Set to logic 1, the counter for RxWait starts only if an external RF field
is detected in Target mode for NFCIP-1 or in Card Communication
mode.
PolSigin defines the polarity of the SIGIN pin. Set to logic 1, the
polarity of SIGIN pin is active high. Set to logic 0 the polarity of SIGIN
pin is active low.
Note: The internal envelope signal is coded active low.
Note: Changing this bit will generate a SiginActIRq event.
Set to logic 1, the internal mode detector is switched off.
Note: The mode detector is only active during the AutoColl command.
Defines the preset value for the CRC co-processor for the command
CalCRC.
Note: During any communication, the preset values is selected
automatically according to the definition in the bits RxMode and
TxMode.
Value
00
01
10
11
111336
Description
0000
6363
A671
FFFF
r/w
5
r/w
4
r/w
3
Transmission module
r/w
2
© NXP B.V. 2011. All rights reserved.
PN512
CRCPreset
r/w
1
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r/w
0

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