EP2SGX90EF1152I4 Altera, EP2SGX90EF1152I4 Datasheet - Page 24
EP2SGX90EF1152I4
Manufacturer Part Number
EP2SGX90EF1152I4
Description
Stratix II GX
Manufacturer
Altera
Datasheet
1.EP2SGX90EF1152I4.pdf
(316 pages)
Specifications of EP2SGX90EF1152I4
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Not Compliant
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Price
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Transceivers
2–16
Stratix II GX Device Handbook, Volume 1
Figure 2–13. Programmable Receiver Termination
If a design uses external termination, the receiver must be externally
terminated and biased to 0.85 V or 1.2 V.
of an external termination and biasing circuit.
Figure 2–14. External Termination and Biasing Circuit
Programmable Equalizer
The Stratix II GX receivers provide a programmable receive equalization
feature to compensate the effects of channel attenuation for high-speed
signaling. PCB traces carrying these high-speed signals have low-pass
filter characteristics. The impedance mismatch boundaries can also cause
signal degradation. The equalization in the receiver diminishes the lossy
attenuation effects of the PCB at high frequencies.
50/60/75- Ω
Termination
Resistance
Transmission
Line
50, 60, or 75 Ω
50, 60, or 75 Ω
V
Receiver External Termination
and Biasing
DD
× {R2/(R1 + R 2)} = 0.85/1.2 V
Receiver External Termination
R1/R2 = 1K
V
C1
and Biasing
DD
V
CM
Figure 2–14
R2
R1
Stratix II GX Device
shows an example
Differential
Altera Corporation
Buffer
RXIN
RXIP
Input
Receiver
October 2007
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