EP2SGX90EF1152I4 Altera, EP2SGX90EF1152I4 Datasheet - Page 77

Stratix II GX

EP2SGX90EF1152I4

Manufacturer Part Number
EP2SGX90EF1152I4
Description
Stratix II GX
Manufacturer
Altera
Datasheet

Specifications of EP2SGX90EF1152I4

Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Not Compliant

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0
TriMatrix
Memory
Altera Corporation
October 2007
Column IOE
Row IOE
Maximum performance
True dual-port memory
Simple dual-port memory
Single-port memory
Shift register
ROM
FIFO buffer
Pack mode
Byte enable
Address clock enable
Parity bits
Mixed clock mode
Memory initialization (.mif)
Table 2–18. Stratix II GX Device Routing Scheme (Part 2 of 2)
Table 2–19. TriMatrix Memory Features (Part 1 of 2)
Memory Feature
Source
TriMatrix memory consists of three types of RAM blocks: M512, M4K,
and M-RAM. Although these memory blocks are different, they can all
implement various types of memory with or without parity, including
true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO
buffers.
blocks.
M512 RAM Block
(32 × 18 Bits)
500 MHz
Table 2–19
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v
v
v
v
v v v v
shows the size and features of the different RAM
M4K RAM Block
(128 × 36 Bits)
Destination
550 MHz
v v
Stratix II GX Device Handbook, Volume 1
v
v
v
v
v
v
v
v
v
v
v
v
Stratix II GX Architecture
(4K × 144 Bits)
M-RAM Block
420 MHz
v
v
v
v
v
v
v
v
v
(1)
2–69

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