EP2SGX90EF1152I4 Altera, EP2SGX90EF1152I4 Datasheet - Page 41

Stratix II GX

EP2SGX90EF1152I4

Manufacturer Part Number
EP2SGX90EF1152I4
Description
Stratix II GX
Manufacturer
Altera
Datasheet

Specifications of EP2SGX90EF1152I4

Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Not Compliant

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Figure 2–26. Stratix II GX Block in Reverse Serial Loopback Mode
Altera Corporation
October 2007
FPGA
Logic
Array
Transmitter Digital Logic
Receiver Digital Logic
Incremental
Incremental
Generator
RX Phase
Compen-
Verify
BIST
BIST
sation
FIFO
Compensation
TX Phase
FIFO
Ordering
Serializer
Byte
Byte
Figure 2–26
Reverse Serial Pre-CDR Loopback
The reverse serial pre-CDR loopback mode uses the analog portion of the
transceiver. An external source (pattern generator or transceiver)
generates the source data. The high-speed serial source data arrives at the
high-speed differential receiver input buffer, loops back before the CRU
unit, and is transmitted though the high-speed differential transmitter
output buffer. It is for test or verification use only to verify the signal
being received after the gain and equalization improvements of the input
buffer. The signal at the output is not exactly what is received since the
signal goes through the output buffer and the VOD is changed to the
VOD setting level. The pre-emphasis settings have no effect.
20
serializer
Byte
De-
Encoder
8B/10B
shows the data path in reverse serial loopback mode.
Decoder
8B/10B
Generator
PRBS
BIST
Match
Rate
FIFO
Stratix II GX Device Handbook, Volume 1
Deskew
FIFO
PRBS
Verify
BIST
Aligner
Word
Stratix II GX Architecture
Analog Receiver and
Transmitter Logic
Serializer
serializer
De-
Reverse
Serial
Loopback
Recovery
Clock
Unit
2–33

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