EP2SGX90EF1152I4 Altera, EP2SGX90EF1152I4 Datasheet - Page 290

• Manufacturer Part Number: EP2SGX90EF1152I4
• Description: Stratix II GX
• Manufacturer: Altera

Specifications of EP2SGX90EF1152I4

• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Not Compliant

Tables 4–98
derivation for different I/O standards on Stratix II GX devices. Examples
are also provided that show how to calculate DCD as a percentage.
Here is an example for calculating the DCD as a percentage for a
non-DDIO output on a row I/O on a -3 device:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum
DCD is 95 ps (see
period T is:
To calculate the DCD as a percentage:
3.3-V LVTTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS
Row I/O Output Standard
Table 4–98. Maximum DCD for Non-DDIO Output on Row I/O Pins
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps
(T/2 – DCD) / T = (3,745 ps/2 – 95 ps) / 3,745 ps = 47.5% (for low
boundary)
(T/2 + DCD) / T = (3,745 ps/2 + 95 ps) / 3,745 ps = 52.5% (for high
boundary)
through
Table
4–105
4–99). If the clock frequency is 267 MHz, the clock
show the maximum DCD in absolution
-3 Devices
Maximum DCD (ps) for Non-DDIO Output
245
125
105
180
165
115
95
55
80
85
55
-4 and -5 Devices
275
155
135
180
195
145
125
100
115
85
80
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps