LAN9313-NZW SMSC, LAN9313-NZW Datasheet - Page 144

Ethernet ICs Three Port 10/100 Ethernet Switch

LAN9313-NZW

Manufacturer Part Number
LAN9313-NZW
Description
Ethernet ICs Three Port 10/100 Ethernet Switch
Manufacturer
SMSC
Type
Three Port Managed Ethernet Switchr
Datasheet

Specifications of LAN9313-NZW

Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Switches
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 Mbps, 100 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
0 V
Supply Current (max)
155 mA, 270 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
LAN9313-NZW
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Microchip Technology
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Part Number:
LAN9313-NZW
Manufacturer:
SMSC
Quantity:
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Revision 1.7 (06-29-10)
12.2.2.2
12.3
nP2LED3
nP2LED2
nP2LED1
nP2LED0
nP1LED3
nP1LED2
(GPIO7)
(GPIO6)
(GPIO5)
(GPIO4)
(GPIO3)
(GPIO2)
GPIO_INT_POL[9:8] bits also determine the polarity of the clock events as described in
Section
IEEE 1588 GPIO Interrupts
In addition to the standard GPIO interrupts in the
Register
to generate and clear specific IEEE 1588 related interrupts. When GPIO 9 or GPIO 8 are enabled as
inputs and an active edge occurs, the IEEE 1588 clock capture is indicated by the 1588_GPIO9_INT
and 1588_GPIO8_INT interrupts respectively in the
(1588_INT_STS_EN). These interrupts are enabled by setting the corresponding 1588_GPIO9_EN
and 1588_GPIO8_EN bits in the
GPIO inputs must be active for greater than 40nS to be recognized as capture events.
When GPIO 8 and GPIO 9 are enabled, the 1588 Timer Interrupt bit (1588_TIMER_INT) of the
Interrupt Status and Enable Register (1588_INT_STS_EN)
GPIO[9:8]. A clear is only registered when the GPIO input is active for greater than 40nS.
Eight pins, GPIO[7:0], are shared with LED functions (nP1LED[3:0] and nP2LED[3:0]). These pins are
configured as LED outputs by setting the corresponding LED_EN bit in the
(LED_CFG). When configured as a LED, the pin is an open-drain, active-low output and the GPIO
related input buffer and pull-up are disabled. The LED outputs are always active low. As a result, a
low signal on the LED pin equates to the LED “on”, and a high signal equates to the LED “off”.
The functions associated with each LED pin are configurable via the LED_FUN[1:0] bits of the
Configuration Register
various port related functions. These functions are described in
definition of each indication type.
The default values of the LED_FUN[1:0] and LED_EN[7:0] bits of the
(LED_CFG)
For more information on the
Section 13.1.2.4, "LED Configuration Register (LED_CFG)," on page
LED Operation
Full-duplex / Collision
Link / Activity
Link / Activity
12.2.1.2.
(GPIO_INT_STS_EN), the IEEE 1588 timestamp enabled GPIO[9:8] pins contain the ability
Speed
Port 0
Port 2
Port 2
Port 2
Port 0
Port 1
are determined by the LED_fun_strap[1:0] and LED_en_strap[7:0] configuration straps.
00b
RX
TX
Table 12.1 LED Operation as a Function of LED_CFG[9:8]
(LED_CFG). These bits allow the configuration of each LED pin to indicate
Full-duplex / Collision
LED Configuration Register (LED_CFG)
100Link / Activity
100Link / Activity
10Link / Activity
1588 Interrupt Status and Enable Register
DATASHEET
LED_CFG[9:8] (LED_FUN[1:0])
Port 0
Port 2
Port 2
Port 2
Port 0
Port 1
01b
RX
TX
144
General Purpose I/O Interrupt Status and Enable
Full-duplex / Collision
1588 Interrupt Status and Enable Register
Activity
Activity
Speed
Port 2
Port 2
Port 2
Port 2
Port 1
Port 1
Three Port 10/100 Managed Ethernet Switch with MII
can be cleared by an active edge on
Link
Link
10b
Table 12.1
159.
and its related straps, refer to
LED Configuration Register
LED Configuration Register
SMSC LAN9313/LAN9313i
followed by a detailed
(1588_INT_STS_EN).
Port 2
RXDV
Port 2
Port 0
RXDV
Port 0
TXEN
TXEN
11b
-
-
Datasheet
1588
LED

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