LAN9313-NZW SMSC, LAN9313-NZW Datasheet - Page 230

• Manufacturer Part Number: LAN9313-NZW
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7 (06-29-10)
13.1.8.7
BITS
31:4
3
2
1
0
RESERVED
Virtual PHY Reset (VPHY_RST)
Setting this bit resets the Virtual PHY. When the Virtual PHY is released from
reset, this bit is automatically cleared. All writes to this bit are ignored while
this bit is set.
Note:
Port 2 PHY Reset (PHY2_RST)
Setting this bit resets the Port 2 PHY. The internal logic automatically holds
the PHY reset for a minimum of 102uS. When the Port 2 PHY is released
from reset, this bit is automatically cleared. All writes to this bit are ignored
while this bit is set.
Note:
Port 1 PHY Reset (PHY1_RST)
Setting this bit resets the Port 1 PHY. The internal logic automatically holds
the PHY reset for a minimum of 102uS. When the Port 1 PHY is released
from reset, this bit is automatically cleared. All writes to this bit are ignored
while this bit is set.
Note:
Digital Reset (DIGITAL_RST)
Setting this bit resets the complete chip except the PLL, Virtual PHY, Port 1
PHY, and Port 2 PHY. The EEPROM Loader will automatically reload the
configuration following this reset, but will not reset the Virtual PHY, Port 1
PHY, or Port 2 PHY. If desired, the above PHY resets can be issued once
the device is configured. All system CSRs are reset except for any NASR
type bits. Any in progress EEPROM commands (including RELOAD) are
terminated.
When the chip is released from reset, this bit is automatically cleared. The
BYTE_TEST register should be polled to determine when the reset is
complete. All writes to this bit are ignored while this bit is set.
Note:
Reset Control Register (RESET_CTL)
This register contains software controlled resets.
Note: This register can be read while the LAN9313/LAN9313i is in the not ready state. This register
Note: In SMI mode, either half of this register can be read without the need to read the other half.
This bit is not accessible via the EEPROM Loader.
This bit is not accessible via the EEPROM Loader.
This bit is not accessible via the EEPROM Loader.
This bit is not accessible via the EEPROM Loader.
can also be polled while the device is in the reset state without causing any damaging effects.
However, the returned data will be invalid since the serial interfaces are also in the reset state
at this time.
Offset:
1F8h
DESCRIPTION
DATASHEET
230
Size:
Three Port 10/100 Managed Ethernet Switch with MII
32 bits
TYPE
R/W
R/W
R/W
R/W
SMSC LAN9313/LAN9313i
RO
SC
SC
SC
SC
DEFAULT
Datasheet
0b
0b
0b
0b
-