KSZ8995MA B3 Micrel Inc, KSZ8995MA B3 Datasheet - Page 19

• Manufacturer Part Number: KSZ8995MA B3
• Manufacturer: Micrel Inc

Specifications of KSZ8995MA B3

• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Semptember 2008
Notes:
1.
Pin Number
114
113
115
119
P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
NC = No connect.
57
55
54
53
52
51
56
47
48
11
20
26
33
10
19
25
32
84
87
5
4
PWRDN_N
RESERVE
Pin Name
PMTXEN
PMTXER
SCANEN
PMTXD0
PMTXD1
PMTXD2
PMTXD3
SCONF0
PMTXC
RST_N
RXM1
RXM2
RXM3
RXM4
RXM5
RXP1
RXP2
RXP3
RXP4
RXP5
SCOL
PS0
PS1
Type
Ipd/O
NC
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipu
Ipu
Ipd
Ipd
O
I
I
I
I
I
I
I
I
I
I
(1)
Port
5
5
5
5
5
5
5
1
2
3
4
5
1
2
3
4
5
Pin Function
PHY[5] MII transmit clock. PHY mode MII.
PHY[5] MII transmit bit 0.
PHY[5] MII transmit bit 1.
PHY[5] MII transmit bit 2.
PHY[5] MII transmit bit 3.
PHY[5] MII transmit enable.
PHY[5] MII transmit error.
Serial bus configuration pin. See “Pin 113.”
Serial bus configuration pin. If EEPROM is not present, the
KS8995MA/FQ will start itself with chip default (00)...
Pin Configuration
PS[1:0]=00
PS[1:0]=01
PS[1:0]=10
PS[1:0]=11
Full-chip power down. Active low.
Reserved pin. No connect.
Reset the KS8995MA/FQ. Active low.
Physical receive signal – (differential).
Physical receive signal – (differential).
Physical receive signal – (differential).
Physical receive signal – (differential).
Physical receive signal – (differential).
Physical receive signal + (differential).
Physical receive signal + (differential).
Physical receive signal + (differential).
Physical receive signal + (differential).
Physical receive signal + (differential).
NC for normal operation. Factory test pin.
Switch MII collision detect.
Dual MII configuration pin.
19
Factory Test Mode (BIST)
Serial Bus Configuration
I
Reserved
SPI Slave Mode for CPU Interface
2
C Master Mode for EEPROM
M9999-091508