KSZ8995MA B3 Micrel Inc, KSZ8995MA B3 Datasheet - Page 56

• Manufacturer Part Number: KSZ8995MA B3
• Manufacturer: Micrel Inc

Specifications of KSZ8995MA B3

• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Semptember 2008
Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in MAC pause control frames.
Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or the MIB counters.
Note:
Write to Register 111 will actually trigger a command. Read or write access will be decided by bit 4 of Register 110.
Address
Register 101 (0x65): TOS Priority Control Register 5
7-0
Register 102 (0x66): TOS Priority Control Register 6
7-0
Register 103 (0x67): TOS Priority Control Register 7
7-0
Address
Register 104 (0x68): MAC Address Register 0
7-0
Register 105 (0x69): MAC Address Register 1
7-0
Register 106 (0x6A): MAC Address Register 2
7-0
Register 107 (0x6B): MAC Address Register 3
7-0
Register 108 (0x6C): MAC Address Register 4
7-0
Register 109 (0X6D): MAC Address Register 5
7-0
Address
Register 110 (0x6E): Indirect Access Control 0
7-5
4
3-2
1-0
Register 111 (0x6F): Indirect Access Control 1
7-0
Address
Register 112 (0x70): Indirect Data Register 8
68-64
Name
DSCP[23:16]
DSCP[15:8]
DSCP[7:0]
Name
MACA[47:40]
MACA[39:32]
MACA[31:24]
MACA[23:16]
MACA[15:8]
MACA[7:0]
Indirect Data
Reserved
Read High Write Low
Table Select
Indirect Address High
Name
Name
Indirect Address Low
Description
Description
Description
Bit 68-64 of indirect data.
Description
Reserved.
1, read cycle.
0, write cycle.
00 = static mac address table selected.
01 = VLAN table selected.
10 = dynamic address table selected.
11 = MIB counter selected.
Bit 9-8 of indirect address.
Bit 7-0 of indirect address.
56
Mode
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
Mode
R/W
R/W
R/W
R/W
R/W
R/W
M9999-091508
00000000
00000000
00000000
Default
Default
00000000
Default
Default
0x00
0x10
0xA1
00000
0xff
0xff
0xff
000
00
0
0