KSZ8995MA B3 Micrel Inc, KSZ8995MA B3 Datasheet - Page 3

• Manufacturer Part Number: KSZ8995MA B3
• Manufacturer: Micrel Inc

Specifications of KSZ8995MA B3

• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Semptember 2008
Features
• Integrated switch with five MACs and five fast
• Shared memory based switch fabric with fully non-
• 1.4Gbps high-performance memory bandwidth
• 10BASE-T, 100BASE-TX, and 100BASE-FX modes
• Dual MII configuration: MII-Switch (MAC or PHY
• IEEE 802.1q tag-based VLAN (16 VLANs, full-range
• VLAN ID tag/untag options, per-port basis
• Programmable rate limiting 0Mbps to 100Mbps,
• Flow control or drop packet rate limiting (ingress port)
• Integrated MIB counters for fully compliant statistics
• Enable/Disable option for huge frame size up to 1916
• IGMP v1/v2 snooping for multicast packet filtering
• Special tagging mode to send CPU info on ingress
• SPI slave (complete) and MDIO (MII PHY only) serial
• MAC-id based security lock option
• Control registers configurable on-the-fly (port-priority,
• CPU read access to MAC forwarding table entries
• 802.1d Spanning Tree Protocol
• Port mirroring/monitoring/sniffing: ingress and/or
• Broadcast storm protection with % control – global
• Optimization for fiber-to-copper media conversion
• Full-chip hardware power-down support (register
Ordering Information
Part Number
Standard
KS8995MA
KS8995FQ
KS8995MAI
KS8995FQI
Ethernet transceivers fully compliant to IEEE 802.3u
standard
blocking configuration
mode MII) and MII-P5 (PHY mode MII)
VID) for DMZ port, WAN/LAN separation or inter-
VLAN switch links
ingress and egress port, rate options for high and low
priority, per-port basis in 32Kbps increments
gathering, 34 MIB counters per port
bytes per frame
packet’s port value
management interface for control of register
configuration
802.1p/d/q, AN...)
egress traffic to any port or MII
and per-port basis
configuration not saved)
Pb-Free
KSZ8995MA
KSZ8995FQ
KSZ8995MAI
KSZ8995FQI
–40°C to +85°C
–40°C to +85°C
Temperature
Range
0°C to +70°C
0°C to +70°C
Package
128-Pin PQFP
128-Pin PQFP
128-Pin PQFP
128-Pin PQFP
• Per-port based software power-save on PHY (idle
• QoS/CoS packets prioritization supports: per port,
• 802.1p/q tag insertion or removal on a per-port basis
• MDC and MDI/O interface support to access the MII
• MII local loopback support
• On-chip 64Kbyte memory for frame buffering (not
• Wire-speed reception and transmission
• Integrated look-up engine with dedicated 1K MAC
• Full duplex IEEE 802.3x and half-duplex back
• Comprehensive LED support
• 7-wire SNI support for legacy MAC interface
• Automatic MDI/MDI-X crossover for plug-and-play
• Disable automatic MDI/MDI-X option
• Low power:
• 0.18µm CMOS technology
• Commercial temperature range: 0°C to +70°C
• Industrial temperature range: –40°C to +85°C
• Available in 128-pin PQFP package
Applications
• Broadband gateway/firewall/VPN
• Integrated DSL or cable modem multi-port router
• Wireless LAN access point plus gateway
• Home networking expansion
• Standalone 10/100 switch
• Hotel/campus/MxU gateway
• Enterprise VoIP gateway/phone
• FTTx customer premise equipment
• Managed Media converter
3
link detection, register configuration preserved)
802.1p and DiffServ based
(egress)
PHY control registers (not all control registers)
shared with 1K unicast address table)
addresses
pressure flow control
Core: 1.8V
Digital I/O: 3.3V
Analog I/O: 2.5V or 3.3V
M9999-091508