DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 12

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
12
DPLLCKREF
RPOSD<7...0>
RNEGD<7...0>
RLOS<7...0>
RCLK<7...0>
MTD<7...0>
1. Buf-in = CMOS Input buffer with switching threshold at 3.3V / 2 (V
2. i = <7...0> which corresponds to the E1 channel number
Pin Name
Table 1.
Signal Descriptions
93
89
82
65
75
47
56
40
31
90
83
66
76
46
55
39
30
91
84
67
77
45
54
38
29
88
81
64
74
48
57
41
32
112
115
120
123
130
133
138
141
Pin
BUF-in
BUF-in
BUF-in
BUF-in
BUF-in
HiZ-4ma
PROP
E1 Data and Clocks transmitted to the Multiplexer
E1 Receivers (Transmit side of multiplexer)
E1 Data and Clocks received from the LIU
I
I
I
I
I
O
I/O
High speed PLL clock reference. This is an external 65.536 MHz (+ /-50
ppm) reference clock that can be used in each E1 transmitter as the
Digital Phase Locked Loop Clock input reference. Only needed if an E1
transmitter is configured in jitter attenuation mode.
Positive HDB3 or NRZ Data Receive. Eight E1 data channel inputs
(channel <i>, i=<7..0>) at 2.048 Mbit/s supplied by the E1 line interface
unit(s), in either NRZ or HDB3 format.
Positive HDB3 Data Receive. Eight E1 data channel inputs (channel<i>,
i=<7..0>) at 2.048 Mbit/s supplied by the E1 line interface unit(s), when
HDB3 coding is used. If HDB3 coding is not used, these inputs have to be
grounded.
Loss of Signal from the external line interface unit(s). Eight input
alarms from the E1 line interface circuits (channel<i>, i=<7..0>). RLOS
alarm is active high.
Receive clock inputs. Eight receive E1 clocks at 2.048 MHz provided by
the E1 line interface unit(s).
NRZ Data outputs. Eight E1 data channel outputs of the receivers
(channel<i>, i=<7..0>) at 2.048 Mbit/s transmitted to the multiplexer.
DD
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Description
Datasheet