DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 44

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
4.3.7
4.3.8
4.3.9
44
Bit
<7:4>
Bit 3
Bit 2
Bit 1
Bit 0
Bit <15:13>
Bit <12:0>
Bit <15:10>
Bit <9:0>
Bit
Bit
Bit
Unused
BpvOvrFlwIntEn
RcvRbeOvrFlwEn
RcvCrcOvrFlwIntEn
RcvFasErrOvrFlwEn
Unused
RcvFasErrCnt[12:0]
Unused
RcvCrc4ErrCnt[9:0]
RCV_FRMWD_ERC - Receiver FrameWord Error Counter (j7 - j6H)
(j =[8 to F] and corresponds to the E1 channel number)
(j7H = bits <15:8>, j6H = bits <7:0>)
This counter increments each time an errored E1 frameword (FAS and/or NFAS: see global
configuration register 0FH: bits CnfFeCnt[1..0]) is detected. A write to the MSByte of the counter
(Register j7H) causes the entire counter to be buffered and then cleared. The contents of the buffer
can then be read.
RCV_BLCK_ERC - Receiver CRC-4 Block Error Counter (j9 - j8H)
(j =[8 to F] and corresponds to the E1 channel number)
(j9H = bits<15:8>, j8H = bits <7:0>
This counter increments each time either a CRC Block error event is selected. A write to the
MSByte of the counter (Register j9H) causes the entire counter to be buffered and then cleared.
The contents of the buffer can then be read.
RCV_RMT_BLCK_ERC - Receiver Remote CRC-4 Block Error Counter
(jB - jAH)
(j =[8 to F] and corresponds to the E1 channel number)
(jBH = bits<15:8>, jAH = bits<7:0>)
Name
Name
Name
Label
Label
Label
Type
Type
RO
RO
Type
R/W
R/W
R/W
R/W
Datasheet
Default
Default
Default
0
0
0
0
0
0