DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 39

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

4.2.8
4.2.9
4.2.10
Datasheet
Bit <15:13>
Bit <12:0>
Bit <15:10> Unused
Bit <9:0>
Bit < 15:10>
Bit <9:0>
Bit
Bit
Bit
XmtCrc4ErrCnt[9:0]
Unused
XmtFasErrCnt[12:0]
Unused
XmtRbeCnt[9:0]
XMT_BLCK_ERC - Transmitter CRC-4 Block Errors Counter
(i9H - i8H)
(i = [0 to 7] and corresponds to the E1 channel number)
(i9H = bits<15:8>, i6H = bits<7:0>
This counter increments each time a CRC-4 Block error is detected. A write to the MSByte of the
counter (register i9H) causes the entire counter to be buffered and then cleared. The contents of the
buffer can then be read.
XMT_RMT_ERC - Transmitter Remote CRC-4 Block Errors Counter
(iB - iAH)
(i = [0 to 7] and corresponds to the E1 channel number)
(iBH = bits<15:8>, iAH = bits<7:0>)
This counter increments each time a Remote CRC-4 Block error is detected. A write to the MSByte
of the counter (register iBH) causes the entire counter to be buffered and then cleared. The contents
of the buffer can then be read.
XMT_RETMBUF - Transmitter Retiming Buffer Positive & Negative
Slip Counters (iCH)
(i = [0 to 7] and corresponds to the E1 channel number)
A write to the register (register iC) causes both counters to be buffered and then cleared. The
contents of the buffer can then be read.
Name
Name
Name
Label
Label
Label
Type
RO
RO
Type
RO
Type
00H
Default
LXT6282
Default
Default
0
00H
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