DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 36

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
4.2.2
4.2.3
36
Bit 3
Bit
<2:1>
Bit 0
Bit <7:5>
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
OpCnf <1..0>
XmtLnCodeSel
XmtCrc-4En
Unused
XmtRmtAlm
XmtLomf
XmtOof
XmtAisDet
Unused
Name
Name
XMT_ALRM_INTO - Transmitter Alarm Interrupt 0 (i1H)
(i = [0 to 7] and corresponds to the E1 channel number)
This register identifies the interrupt source for a particular E1 Channel Transmitter. Each of these
bits can cause the chip interrupt pin to become active if enabled via the bits in the Transmit
Interrupt Enable Register 0 (i4H).
XMT_ALRM_INT1 - Transmitter Alarm Interrupt 1(i2H)
(i = [0 to 7] and corresponds to the E1 channel number)
This register identifies the interrupt source for a particular E1 Channel Transmitter. Each of these
bits can cause the chip interrupt pin to become active if enabled via the bits in the Transmit
Interrupt Enable Register 1 (i5H).
Enable/disable G704 CRC-4 monitoring and multiframing in the E1 transmitter
(on DTD data input).
0 - Disable. In this case, the E1 transmitter checks the errors in the E1
frameword (every two frames) and counts them in the XmtErrCnt errors
counter. No CRC multiframing
1 - Enable. The chip performs a CRC-4 check on the incoming E1. The blocks
in error is counted in the XmtErrCnt errors counter
Each E1 Transmitter can be configured for the following operational modes.
00 - Passed through mode: no dejitter, no retiming in the transmitter
01 - Dejitter mode
10 - Retiming mode: normal configuration (operates on an E1 framed signal)
11 - Retiming mode: test configuration (operates on a 2.048 Mbit/s un-framed
signal; in this mode the CRC-4, REBE and remote alarm monitoring functions
are irrelevant since the incoming data is supposed to be un-framed.)
(Note: When not in dejitter mode, the High Speed ADPLL reference Clock is
shut down in the transmitter to save power consumption.)
Line Interface coding (on TPOSD/TNEGD transmit data).
0 - HDB3
1 - NRZ
This bit is set when there is a change in the XmtRmtAlmSt bit (i3H). It
is cleared when status register (i3H) is read.
This bit is set when there is a change in the XmtLomfSt bit (i3H). It is
cleared when status register (i3H) is read.
This bit is set when there is a change in the XmtOofSt bit (i3H). It is
cleared when status register (i3H) is read.
This bit is set when there is a change in the XmtAisDetSt bit (i3H). It is
cleared when status register (i3H) is read.
Label
Label
Type
RO
RO
RO
RO
Type
R/W
R/W
R/W
Datasheet
Default
Default
0
0
0
0
01
0
0