DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 52

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
6.0
6.1
.
52
JTDI
JTMS
JTCK
JTRS
Table 13. JTAG Pin Description
Figure 12. Test Access Port
Testability
The LXT6282 provides a method for enhancing testability: IEEE1149.1 Boundary Scan (JTAG) is
used for testing of the interconnect.
IEEE 1149.1 Boundary Scan Description
The boundary scan circuitry allows the user to test the interconnection between the LXT6282 and
the circuit board. The boundary scan port consists of 5 pins as shown in
scan circuitry is the Test Access Port controller (TAP). The TAP controller is a 16 state machine
that controls the function of the boundary scan circuitry. Inputs of the TAP controller are the Test
Mode Select (JTMS) and the Test Clock (JTCK) signals. Data and instructions are shifted into the
LXT6282 through the Test Data In pin (JTDI). Data and instructions are shifted out through the
Test Data Out pin (JTDO). An asynchronous reset pin (JTRS) allows to reset the boundary scan
circuitry
Pin #
103
104
102
101
100
JTMS_P
JTCK_P
JTRS_P
JTDO_P
JTDI_P
Name
Test Access Port Controller
I/O
O
I
I
I
I
Instruction Register
Device ID Register
Test Mode Select: Determines state of TAP Controller. Pull up 48k
Test Clock: Clock for all boundary scan circuitry
Test Reset: Active low asynchronous signal that causes the TAP controller to reset.
Pull down 35k
Test Data In: Input signal used to shift in instructions and data. Pull up 48k
Test data Out: Output signal used to shift out instructions and data.
Bypass Register
Boundary Scan
Function
Table
13. The heart of the
Datasheet
JTDO