WBLXT9785HC.D0-865113 Cortina Systems Inc, WBLXT9785HC.D0-865113 Datasheet - Page 108

• Manufacturer Part Number: WBLXT9785HC.D0-865113
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HC.D0-865113

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 39
Cortina Systems
BGA15 Signal Descriptions (Sheet 3 of 7)
®
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. Switched to TPIP/N Inputs when MDIX is not active (twisted-pair, non-crossover MDI mode).
3. Switched to TPOP/N Outputs when MDIX is not active (twisted-pair, non-crossover MDI mode).
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
TPOP0, TPON0
TPOP1, TPON1
TPOP2, TPON2
TPOP3, TPON3
TPOP4, TPON4
TPOP5, TPON5
TPOP6, TPON6
TPOP7, TPON7
TPIP0, TPIN0
TPIP1, TPIN1
TPIP2, TPIN2
TPIP3, TPIN3
TPIP4, TPIN4
TPIP5, TPIN5
TPIP6, TPIN6
TPIP7, TPIN7
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
TRST_L
Symbol
MDC
TDO
TMS
TCK
TDI
Designation
BGA15 Ball
M14, M13,
G14, G13,
P13, N13,
N14, P14,
P12, N12,
H14, H13,
D13, D14,
C14, C13,
K13, K14,
F14, F13,
E13, E14,
B14, A14,
A13, B13
L13, L14,
A12, B12
J14, J13,
C12
A10
C11
B11
A11
P4
Network Interface Signal Description
Miscellaneous Signal Description
JTAG Test Signal Description
I, ST, ID
I, ST, IP
I, ST, IP
I, ST, ID
I, ST, IP
AO/AI
AI/AO
O, TS
Type
Signal Description
Management Data Clock.
Clock for the MDIO serial data channel. Maximum
frequency is 20 MHz. Only MDC0 is used when 1x8 port
sectionalization is selected.
mode, MDC0 clocks ports 0-3 register accesses and MDC1
clocks ports 4-7 register accesses. Refer to
page
Twisted-Pair Outputs
During 100BASE-TX or 10BASE-T operation, TPO pins
drive 802.3 compliant pulses onto the line.
Twisted-Pair Inputs
During 100BASE-TX or 10BASE-T operation, TPI pins
receive differential 100BASE-TX or 10BASE-T signals from
the line.
Test Data Input.
Test data sampled with respect to the rising edge of TCK.
Test Data Output.
Test data driven with respect to the falling edge of TCK.
Test Mode Select.
Test Clock.
Clock input for JTAG test.
Test Reset.
Reset input for JTAG test.
136.
3
, Positive & Negative, Ports 0-7.
2
, Positive & Negative, Ports 0-7.
3.6 BGA15 Signal Descriptions
In 2x4 port sectionalization
Figure 21 on
Page 108