WBLXT9785HC.D0-865113 Cortina Systems Inc, WBLXT9785HC.D0-865113 Datasheet - Page 133

• Manufacturer Part Number: WBLXT9785HC.D0-865113
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HC.D0-865113

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.7.4
4.7.4.1
4.7.4.2
4.7.4.3
4.7.4.4
4.7.5
Figure 19
Cortina Systems
Receive Data Stream
Receive data and control information are signalled in ten-bit segments. In 100 Mbps
mode, each segment contains a new byte of data. In 10 Mbps mode, each segment is
repeated ten times (except for the CRS bit), and the MAC can sample any of the ten
segments.
Carrier Sense
The CRS bit (slot 0) is generated when a packet is received from the network interface.
The CRS bit is set in real time, even in 10 Mbps mode (all other bits are repeated in 10
sequential segments).
Receive Data Valid
The LXT9785/LXT9785E asserts the RX_DV bit (slot 1) when it receives a valid packet.
The assertion timing changes depending on line operating speed:
Receive Error
When the LXT9785/LXT9785E receives an invalid symbol from the network in 100BASE-
TX mode, it drives “0101” on the associated RxData signals.
Receive Status Encoding
The LXT9785/LXT9785E encodes status information onto the RxData line during IPG as
seen in
nibble (RxData<7:4> of the last byte of the previous frame). RxData and RX_DV are
passed through the internal elasticity FIFO to smooth any clock rate differences between
the recovered clock and the 125 MHz reference clock.
Collision
The SMII interface does not provide a collision output and relies on the MAC to interpret
COL conditions using CRS and TxEN. CRS is unaffected by the transmit path.
Serial MII Receive Synchronization
®
• For 100BASE-TX and 100BASE-FX links, the RX_DV bit is asserted from the first
• For 10BASE-T links, the entire preamble is truncated. The RX_DV bit is asserted with
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
CLOCK
RxSYNC
nibble of preamble to the last nibble of the data packet.
the first nibble of the Start-of-Frame Delimiter (SFD) “5D” and remains asserted until
the end of the packet.
RX
Table 44 on page
CRS
RX_DV
134. Status bit RxData<5> indicates the validity of the upper
RXD0
RXER
RXD1
Speed
RXD2
Duplex
RXD3
Link
RXD4
J abber
RXD5
Valid
4.7 Serial MII Operation
RXD6
FCE
RXD7
RXD7
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CRS