WBLXT9785HC.D0-865113 Cortina Systems Inc, WBLXT9785HC.D0-865113 Datasheet - Page 177

• Manufacturer Part Number: WBLXT9785HC.D0-865113
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HC.D0-865113

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 64
Figure 43
Table 65
Cortina Systems
SMII - 100BASE-FX Transmit Timing Parameters
SMII - 10BASE-T Receive Timing
SMII - 10BASE-T Receive Timing Parameters (Sheet 1 of 2)
®
SYNC setup to REFCLK rising edge and
TxData setup to REFCLK rising edge
SYNC hold from REFCLK rising edge
and TxData hold from REFCLK rising
edge
TxEN sampled to start of /J/
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Note:
RxData output delay from
REFCLK rising edge
RxData Rise/Fall Time
Receive Start-of-Frame to CRS
asserted
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Assumes each SMII segment is sampled for CRS.
3. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Note:
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
testing.
100BASE-TX or 100BASE-FX).
testing.
100BASE-TX or 100BASE-FX).
REFCLK
RxData
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
SYNC
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
TPFI
Parameter
Parameter
t
3
t1
t2
t3
Sym
t
5
1.5
–
–
Min
Sym
t1
t2
t3
t
6
–
1
17
Typ1
Min
1.5
1.0
–
t
1
5
–
21
Max
Typ1
10
–
–
ns
ns
BT
Units
t
3
2
Max
17
–
–
Minimum C
Maximum C
Synchronous sampling of SMII
Units
BT
ns
ns
Test Conditions
6.0 Test Specifications
2
t
4
L
L
= 5 pF
= 20 pF
Test Conditions
–
–
–
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