WBLXT9785HC.D0-865113 Cortina Systems Inc, WBLXT9785HC.D0-865113 Datasheet - Page 122

• Manufacturer Part Number: WBLXT9785HC.D0-865113
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HC.D0-865113

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.4
4.4.1
4.4.2
4.4.2.1
4.4.2.2
4.4.2.3
4.4.2.4
Cortina Systems
Operating Requirements
Power Requirements
The LXT9785/LXT9785E requires four power supply inputs: VCCD, VCCA, VCCPECL
and VCCIO. The digital and analog circuits require 2.5 V supplies (VCCD, VCCR, and
VCCT). These inputs may be supplied from a single source although decoupling is
required to each respective ground. The fiber VCCPECL supply can be connected to
either 2.5 V or 3.3 V.
A separate power supply may be used for the MII, JTAG and MDIO (VCCIO) interfaces.
The power supply may be either +2.5 V or +3.3 V. VCCIO should be supplied from the
same power source used to supply the controller on the other side of the interface. Refer
to
page
page
for I/O characteristics.
As a matter of good practice, these supplies should be as clean as possible. Typical
filtering and decoupling are shown in
be brought up as close to the same time as possible. However, there are no specific
timing requirements.
Clock/SYNC Requirements
Reference Clock
The LXT9785/LXT9785E requires a constant enabled reference clock (REFCLK).
REFCLK’s frequency must be 50 MHz for RMII or 125 MHz for SMII/SS-SMII. The
reference clock is used to generate transmit signals and recover receive signals. A
crystal-based clock is recommended over a derived clock (that is, PLL-based) to minimize
transmit jitter. Refer to
timing requirements.
For applications that use a single 8-port sectionalization, REFCLK0 and REFCLK1 must
always be tied together and to the source. In 2x4 applications, REFCLK0 and REFCLK1
are not tied together.
TxCLK Signal (SS-SMII only)
The LXT9785/LXT9785E requires a 125 MHz input transmit clock synchronous with
TxDatan and frequency locked to REFCLK. See
TxSYNC Signal (SMII/SS-SMII)
The LXT9785/LXT9785E requires a 12.5 MHz input pulse for SMII synchronization. See
Figure 22 on page
RxSYNC Signal (SS-SMII only)
The LXT9785/LXT9785E provides a 12.5 MHz output pulse synchronous with the
RxDatan outputs. See
®
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 54, Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/- 5%), on
171,
172, and
Table 55, Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%), on
Table 56, Digital I/O DC Electrical Characteristics – SD Pins, on page 172
137.
Table 57, Required Clock Characteristics, on page 172
Figure 23 on page
Figure 34 on page
137.
Figure 22 on page
165. The power supplies should
4.4 Operating Requirements
137.
for clock
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