WBLXT9785HC.D0-865113 Cortina Systems Inc, WBLXT9785HC.D0-865113 Datasheet - Page 161

• Manufacturer Part Number: WBLXT9785HC.D0-865113
• Manufacturer: Cortina Systems Inc

Specifications of WBLXT9785HC.D0-865113

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
5.0
5.1
5.2
5.2.1
Cortina Systems
Application Information
Design Recommendations
The LXT9785/LXT9785E is designed to comply with IEEE 802.3 requirements to provide
outstanding receive Bit Error Rate (BER), and long-line-length performance. To achieve
maximum performance from the LXT9785/LXT9785E, attention to detail and good design
practices are required. Refer to the Cortina Systems
8-Port 10/100 Mbps PHY Transceivers Design and Layout Guide application note for
detailed design and layout information.
General Design Guidelines
Adherence to generally accepted design practices is essential to minimize noise levels on
power and ground planes. Up to 50 mV maximum of noise is considered acceptable.
High-frequency switching noise can be reduced, and its effects eliminated, by following
these simple guidelines throughout the design:
Power Supply Filtering
Power supply ripple and digital switching noise on the VCC plane may cause EMI
problems and degrade line performance. The best approach to this problem is to minimize
ground noise as much as possible using good general techniques and by filtering the VCC
plane. It is generally difficult to predict in advance the performance of any design,
although certain factors greatly increase the risk of having problems:
Cortina recommends filtering the power supply to the analog VCC pins of the LXT9785/
LXT9785E. This has two benefits. First, it keeps digital switching noise out of the analog
circuitry inside the LXT9785/LXT9785E, helping with line performance. Second, if the
VCC planes are laid out correctly, digital switching noise is kept away from external
connectors, reducing EMI problems.
®
• Fill in unused areas of the signal planes with solid copper and attach them with vias to
• Use ample bulk and decoupling capacitors throughout the design (a value of 0.01μF
• Provide ample power and ground planes.
• Provide termination on all high-speed switching signals and clock lines.
• Provide impedance matching on long traces to prevent reflections.
• Route high-speed signals next to a continuous, unbroken ground plane.
• Filter and shield DC-DC converters, oscillators, etc.
• Do not route any digital signals between the LXT9785/LXT9785E and the RJ-45
• Do not extend any circuit power and ground plane past the center of the magnetics or
• Poorly-regulated or over-burdened power supplies.
• Wide data busses (32-bits+) running at a high clock rate.
• DC-to-DC converters.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
a VCC or ground plane that is not located adjacent to the signal layer.
is recommended for decoupling caps).
connectors at the edge of the board.
to the edge of the board. Use this area for chassis ground, or leave it void.
®
LXT9785 and LXT9785E Advanced
5.0 Application Information
Page 161