M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 45

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
2.22 Automatic Response Control Register
R e v 1 . 0 1
(1) ASCN (SET_CONFIGURATION Automatic Response Mode) Bit (b1)
(2) ASAD (SET_ADDRESS Automatic Response Mode) Bit (b0)
b15
15~2
Automatic Response Control Register (AUTO_RESPONSE_CONTROL)
0
-
-
b
1
0
This bit sets the valid/invalid of automatic response mode for SET_CONFIGURATION request.
With the automatic response mode set to valid, zero-length packet is automatically transmitted against the
requests below at the status stage before notifying the normal completion. Here, the CTRT bit is not set to “1”
(control transfer stage transition interrupt does not occur).
No automatic response is executed when the SET_CONFIGURATION request other than the ones given
above is received. In such case, the CTRT bit is set to “1” (control transfer stage transition interrupt occurs).
When the state gets changed after receiving the aforesaid requests, the DVST bit is set to “1” if the SCFG bit is
set to “1”, irrespective of the validity of this function (device state transition interrupt occurs).
This bit sets the valid/invalid of automatic response mode for SET_ADDRESS request.
With the automatic response mode set to valid, zero-length packet is automatically transmitted against the
requests below at the status stage before notifying the normal completion. Here, the CTRT bit is not set to “1”
(control transfer stage transition interrupt does not occur).
No automatic response is executed when the SET_ADDRESS request other than the ones given above is
received. In such case, the CTRT bit is set to “1” (control transfer stage transition interrupt occurs).
When the state gets changed after receiving the aforesaid requests, the DVST bit is set to “1” if the SADR bit
is set to “1”, irrespective of the validity of this function (device state transition interrupt occurs).
2 0 0 4 . 1 1 . 0 1
SET_CONFIGURATION Automatic Response
Mode
Reserved. Set it to “0”.
ASCN
ASAD
SET_ADDRESS Automatic Response Mode
14
0
-
-
•
•
•
SET_CONFIGURATION request of Configuration Value ≠ 0 in Address state
SET_CONFIGURATION request of Configuration Value = 0 in Configured state
SET_ADDRESS request at Default state
13
0
-
-
p a g e 4 5 o f 1 2 2
12
0
-
-
Bit name
11
0
-
-
10
0
-
-
9
0
-
-
0 :
1 :
0 :
1 :
8
0
-
-
Invalid of automatic response mode for
SET_CONFIGURATION
Valid of automatic response mode for
SET_CONFIGURATION
Invalid of automatic response mode for SET_ADDRESS
Valid of automatic response mode for SET_ADDRESS
7
0
-
-
6
0
-
-
Function
5
0
-
-
4
0
-
-
3
0
-
-
2
0
-
-
<H/W reset : H'0000>
<Address : H’2C>
<USB bus reset : ->
ASCN
<S/W reset : ->
1
0
-
-
R
0
ASAD
b0
0
-
-
W
0