M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 57

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(1) IDLY (Isochronous Transmit Delay Set) Bit (b14)
(2) IVAL (IN Buffer Set/OUT Buffer Status) Bit (b13)
In isochronous transfer, transmission can be started by writing “1” to this bit or to the IVAL bit after writing
the transmit data to the buffer (Note).
When “1” is written to this bit, the data is transmitted by receiving the IN token after confirming the received
SOF packet. After the data transmit starts, this is cleared to “0” (Refer to Figure 2.11).
When “1” is written to the IVAL bit of this register, the data is transmitted by receiving the next IN token
(Refer to Figure 2.12).
This bit indicates valid value when the Creq bit of this register is equal to “0”.
This bit sets/clears the EPB_RDY bit to “1” (Refer to “EPB_RDY bit”).
2 0 0 4 . 1 1 . 0 1
Note:
Note:
When set to OUT buffer (EPi_DIR bit = “0”)
When this bit is set to “1”, the receive data in the CPU side buffer is ready to be read.
This bit is set to “1” due to one of the reasons as follows:
The receive completion is changed by the EPi_RWMD bit.
This bit is cleared to “0” due to one of the reasons as follows:
Set the transmit data size + 1 byte or more to the EPi_MXPS bits. When set to transmit data size, the IVAL bit is
set to “1” when the writing to the buffer completes. Hence, this function is not applicable when set to 1023
bytes, the maximum value of the EPi_MXPS bits.
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
When set to single buffer mode (EPi_DBLB bit = “0”)
When set to double buffer mode (EPi_DBLB bit = “1”)
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p a g e 5 7 o f 1 2 2
Completes receiving (SIE side buffer).
Writes “1” to the TGL bit.
Completes receiving of SIE side buffer and reading of CPU side buffer.
Writes “1” to the TGL bit.
Reads out all the receive data in the CPU side buffer.
Writes “1” to the BCLR bit.
Writes “1” to the ACLR bit.
SO F
SO F
IDLY="1" set
IVAL="1" set
Figure 2.11 Transmit start timing at IDLY bit = “1”
Figure 2.12 Transmit start timing at IVAL bit = “1”
Flame #m
Flame #m
IN
IN
T ransmit start
SO F
Flame #(m+1)
IN
T ransmit start