M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 81

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
3
3.1 Interrupt Function
R e v 1 . 0 1
M66291 OPERATIONS
VBUS
(Vbus Interrupt)
RESM
(Resume Interrupt)
SOFR
(SOF Detect Interrupt)
DVST
(Device State Transition
Interrupt)
CTRT
(Control Transfer Stage
Transition Interrupt)
BEMP
(Buffer Empty / Size Over
Interrupt)
INTN
(Buffer Not Ready Interrupt)
INTR
(Buffer Ready Interrupt)
Registers 0 to 3 are set to interrupt inhibit mode.
There are 8 factors of interrupts in the M66291.
For details, refer to the “Interrupt Status Registers 0 to 3”.
The enable/disable of interrupt can be set by the Interrupt Enable Registers 0 to 3.
Each bit of the Interrupt Status Register is set to “1” according to the factor even if the Interrupt Enable
The list of interrupts in M66291 is given in Table 3.1 and the diagrams related to the interrupt in Figure 3.1.
(Interrupt Name)
2 0 0 4 . 1 1 . 0 1
Status Bit
p a g e 8 1 o f 1 2 2
Change of Vbus input level
(change of "L"->"H", "H"->"L")
Change of USB bus state in suspend state
("J"->"K" or "SE0")
Receive of SOF packet
• Detection of USB bus reset
• Detection of suspend state
• Execution of "SET_ADDRESS"
• Execution of "SET_CONFIGURATION"
• Transition of control write transfer status stage
• Transition of control read transfer status stage
• Completion of control transfer
• Occurrence of control transfer sequence error
• Completion of setup stage
• Transmit of all the data stored in the buffers at each
• Receive of packet exceeding the maximum packet size
When NAK response is automatically executed because
of the buffer not ready state in the IN/OUT token of each
endpoint
When each endpoint is buffer ready state
(read /write enable state)
endpoint
during receiving data packet
Table 3.1 List of Interrupts
Interrupt Factor
Confirmation of Vbus pin input state by the
Vbus bit of the Interrupt Status Register 0
Confirmation of current device state by the
DVSQ bits of the Interrupt Status Register 0
⎯
Confirmation of current device state by the
DVSQ bits of the Interrupt Status Register 0
Confirmation of current control transfer stage
state by the CTSQ bits of the Interrupt Status
Register 0
Confirmation of endpoint number occurred the
interrupt by the EPB_EMP_OVR bits of the
Interrupt Status Register 3
Confirmation of endpoint number occurred
the interrupt by the EPB_NRDY bits of the
Interrupt Status Register 2.
Confirmation of endpoint number of the
occurred interrupt by the EPB_RDY bits of
the Interrupt Status Register 1.
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