M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 48
M66291GP#201
Manufacturer Part Number
M66291GP#201
Description
IC USB CONTROLLER GEN-PUR 48LQFP
Manufacturer
Renesas Electronics America
Datasheet
1.M66291GP201.pdf
(126 pages)
Specifications of M66291GP#201
Package / Case
48-LQFP
Mounting Type
Surface Mount
Current - Supply
30mA
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-20°C ~ 85°C
Interface
Serial
Controller Type
USB 2.0 Controller
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
M 6 6 2 9 1 G P / H P
2.24 EP0_FIFO Control Register
R e v 1 . 0 1
15~14
b15
EP0_FIFO Control Register (EP0_FIFO_CONTROL)
8~0
13
12
11
10
0
-
-
b
9
EP0_PID
2 0 0 4 . 1 1 . 0 1
EP0_PID
Response PID
IVAL
IN Buffer Set/OUT Buffer Status
BCLR
Buffer Clear
E0req
EP0_FIFO Ready
CCPL
Control Transfer Control
Reserved. Set it to “0”.
ODLN
Control Write Receive Data Length
14
0
-
-
IVAL
13
0
-
-
p a g e 4 8 o f 1 2 2
BCLR
12
0
-
-
Bit name
E0req
11
1
-
-
CCPL
10
0
-
-
9
0
-
-
00 : NAK
01 : BUF
1x : STALL
<When set to control write transfer>
0:
1:
Invalid (Ignored when written)
<When set to control read transfer>
0 :
1 :
0 :
1 :
<When set to control write transfer >
0 :
1 :
<When set to control read transfer>
0 :
1 :
0 :
1 :
0 :
1 :
Stores the receive data length in control write transfer
Read
Write
Read
Write
Write
Write
8
0
-
-
(Transmits response PID/data according to the state of
buffer etc,)
Disables the reading of data from the buffer
Enables the reading of data from the buffer
Incomplete to write the data to buffer
Complete to write the data to buffer
Invalid (Ignored when written)
Complete to write the data to buffer
Invalid (Ignored when written)
Buffer clear (When the IVAL bit is set to "1")
Invalid (Ignored when written)
Buffer clear (Note : When the IVAL bit is set to “1”,
make sure to set the EP0_PID bits to “00” before
executing the aforesaid operations.)
Enables to access EP0_FIFO Data Register etc,
Disables to access EP0_FIFO Data Register etc,
NAK response at status stage
Normal completion response at status stage
(ACK response/zero-length packet transmit)
7
(Forced completion : Transmits the short packet)
0
-
-
6
0
-
-
Function
5
0
-
-
ODLN
4
0
-
-
3
0
-
-
2
0
-
-
<H/W reset : H'0800>
<Address : H’32>
<USB bus reset : ->
<S/W reset : ->
1
0
-
-
R
0
0
b0
0
-
-
W
×
0
×