CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 11

• Manufacturer Part Number: CS9211-VNG
• Manufacturer: National Semiconductor

Specifications of CS9211-VNG

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Revision 2.1
Signal Definitions
2.2.3
2.2.4
Signal Name
FLM
VSYNC
DISPOFF#
FP_VDDEN
FP_VCONEN
Signal Name
MA[10:0]
MD[15:0]
Flat Panel Interface Signals (Continued)
Memory Interface Signals
135, 132,
134, 137,
139, 140,
141, 142,
143, 138,
102, 104,
106, 110,
112, 114,
116, 118,
119, 117,
115, 113,
111, 107,
105, 103
Pin No.
Pin No.
136
33
39
34
35
(Continued)
(Drive)
(Drive)
(8 mA)
(8 mA)
(8 mA)
(8 mA)
(8 mA)
(8 mA)
Type
Type
I/O
O
O
O
O
O
Offset
404h[24] = 0
404h[24] = 1
Description
Memory Address Bus
These signals are the address bits to the external frame buffer. Ten bits are
used for EDO (Extended Data Out) DRAM and eleven bits are used for
SDRAM.
Row and column addresses are multiplexed on the same pins.
Memory Data Bus
These bidirectional signals are the external frame buffer data bus.
Offset
Selection
Function
---
---
---
11
Description
First Line Marker (SSTN/DSTN Panels)
This is the frame pulse for the flat panel data indicating a
display frame is about to start.
Depending on the type of panel being interfaced, this signal
can also be referred to as FP or FRAME.
Vertical Sync (TFT Panels)
VSYNC is the vertical sync for active-matrix TFT panel. This
is a delayed version of the input VSYNC signal with the
appropriate pipeline delay relative to the pixel data on
UD[11:0] and LD[11:0].
If pin 33 is selected as VSYNC at Offset 404h[24], its polar-
ity is programmable through Offset 404h[23]:
0 = Active high; 1 = Active low.
Disables Backlight
When this output is asserted low, it turns the backlight off.
Controls LCD VDD FET
When this output is asserted high, VDD voltage is applied
to the panel. This signal is intended to control a power FET
to the LCD panel. The FET may be internal to the panel or
not, depending on the panel manufacturer
Controls LCD Bias Voltage Enable
When this output is asserted high, the contrast voltage is
applied to the panel. This signal should be connected
directly to the panel.
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