CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 12

• Manufacturer Part Number: CS9211-VNG
• Manufacturer: National Semiconductor

Specifications of CS9211-VNG

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Signal Definitions
2.2.4
Signal Name
DQMH
DQML
OE#/BA
RAS#
CASH#
CAS#/CASL#
WE#
MCLK
CKE
CS#
Memory Interface Signals (Continued)
Pin No.
121
120
133
130
124
127
122
123
129
131
(Continued)
(Drive)
(8 mA)
(8 mA)
(8 mA)
(8 mA)
(8 mA)
(8 mA)
(8 mA)
(8 mA)
(8 mA)
Type
mA)
(12
O
O
O
O
O
O
O
O
O
O
Description
Data Input/Output Mask
DQMx is an input mask signal to the frame buffer SDRAM for write accesses
and an output enable signal for read accesses.
• Input data to the SDRAM is masked when DQMx is sampled high during
• The output buffers are placed in a High-Z state (two-clock latency) when
DQMH corresponds to DQ8-DQ15 of the SDRAM.
DQML corresponds to DQ0-DQ7 of the SDRAM.
This signal is not used for EDO DRAM.
Output Enable and Bank Select Address
This pin is the output enable for the DRAM and the bank address selection
for SDRAM.
BA defines to which bank the active, read, write or precharge command is
being applied. This function is not used in the CS9211.
Row Address Strobe
The row address strobe for DRAM/SDRAM.
Column Address Strobe
The column address strobe for the upper byte of EDO DRAM. This pin
should not be connected if SDRAM is used.
Column Address Strobe
The column address strobe for the lower byte of DRAM. This pin should be
connected (to CAS#) if SDRAM is used.
Write Enable
The write enable output for DRAM/SDRAM.
Memory Clock
This clock output from the CS9211 should be connected to the SDRAM. It is
not used for EDO DRAM.
Clock Enable
This output signal should be connected to the SDRAM. When CKE is active
(high), the MCLK signal is low. Deactivating the clock provides precharge
power-down and self-refresh operations (all banks idle), active power-down
(row active CKE in either bank) or clock Suspend operation (burst/access in
progress).
CKE is synchronous to MCLK, except after the device enters power-down
and self refresh modes, where CKE becomes asynchronous until after exit-
ing the same mode. The input buffers, including MCLK, are disabled during
power-down and self refresh modes, and provide low power. CKE may be
tied high.
This signal is not used for EDO DRAM.
Chip Select
This output is connected to the chip select of SDRAM. CS# enables (regis-
tered low) and disables (registered high) the command decoder of the
SDRAM. All commands are masked when CS# is deasserted (high).
a write cycle.
DQMx is sampled high during a read cycle.
12
Revision 2.1