CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 15

• Manufacturer Part Number: CS9211-VNG
• Manufacturer: National Semiconductor

Specifications of CS9211-VNG

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Revision 2.1
Functional Description
3.1.2
As illustrated in Figure 3-3, the connections between the
CS9211 and the LCD panel being driven are simple. There
are three groups of interconnect: Power Control, Timing,
and Data. Because of the wide variety of LCD panels cur-
rently used in the industry, this interface is discussed briefly
and generically.
Power control signals enable the panel’s backlight, main
power, and contrast voltage. In some cases, these signals
may be directly connected to the panel being used; in other
cases, external circuitry such as a power FET, may be
required. Consult the data sheet of the panel being used in
the design for details.
Timing signals are connected directly to the panel. Differ-
ent panel manufacturers use various nomenclatures to
identify the timing signals, some of which are shown (sepa-
rated by the “/” character) in Figure 3-3.
The output of the CS9211 is a 24-bit data bus that is artifi-
cially split into two 12-bit data buses by the CS9211’s
adopted nomenclature (UD/LD). The output data presented
on these buses “moves” from pin to pin depending on the
type of panel being used, as determined by the contents of
several of the CS9211’s internal registers. These output
buses should be thought of as one 24-bit bus for ease of
the designer’s understanding and to avoid confusion with
panels which have a UD/LD-type data bus nomenclature.
3.1.3
The interface between the CS9211 and the frame buffer
memory (if used) is straightforward. Signal names used in
the CS9211 match up with those used by the standard
EDO DRAM and SDRAM devices. Note that the frame
buffer memory is only required for DSTN panels. If the
memory is not required, the memory interface signals from
the CS9211 may remain unconnected.
Panel Connections
Memory Connections
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Graphics
Geode™
CS9211
FP_VCONEN
FLM/VSYNC
FP_VDDEN
Figure 3-3. CS9211 and Flat Panel Signal Connections
DISPOFF#
LP/HSYNC
LDE/MOD
SHFCLK
UD[11:0]
LD[11:0]
(Continued)
15
If a DSTN panel is used, the CS9211 must be connected to
an external frame buffer RAM, which may be either EDO
DRAM or SDRAM. The external frame buffer is not
required if an SSTN panel is used. Pixel data is received by
the pixel port, formatted by a dither block and programma-
ble FRM, and stored in the CS9211 frame buffer. The for-
matted pixel data is subsequently read from the frame
buffer and used to refresh half the DSTN panel, while the
other half receives “live” data from the CS550A.
3.1.4
The CS9211 requires a 14.318 MHz input clock to gener-
ate power sequencing signals to the panel. The input fre-
quency should be 14.318 MHz. The clock may come from a
compatible clock source anywhere in the design, or from a
dedicated crystal oscillator tank circuit. The recommended
oscillator tank circuit is shown in Figure 3-2.
14.318 MHz
Crystal
Crystal Oscillator Interface
Figure 3-2. Oscillator Tank Circuit
Backlight Enable
Panel Main Power Enable
Panel Contrast Voltage Enable
LP/HSYNC/CL1
FLM/VSYNC/FRAME
SF/SHIFT/CL2
LDE(TFT)/MOD(DSTN)
Panel Data (as required)
10 pF
10 pF
LCD Panel
XTALIN
XTALOUT
Companion
Graphics
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CS9211