CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 46

• Manufacturer Part Number: CS9211-VNG
• Manufacturer: National Semiconductor

Specifications of CS9211-VNG

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Register Descriptions
Offset 424h-427h
Offset 428h-42Bh
Offset 42Ch-42Fh
Offset 430h-433h
Offset 434h-437h
31:16
31:16
31:8
31:0
31:8
15:0
5:0
7:2
Bit
15
14
13
12
11
10
1
0
7
6
1
0
9
8
7
6
DITHER_RAM_
RAM_ACCESS
SDRAM_EDO
SDRAM_CLK
FRAME_CNT
GPIO7_DATA
GPIO6_DATA
RAM_ADDR
RAM_UPDT
GPIO7_STS
GPIO6_STS
GPIO5_STS
GPIO4_STS
GPIO3_STS
GPIO2_STS
GPIO1_STS
GPIO0_STS
SIG_DATA
DITHER_
DITHER_
DITHER_
_INVERT
SIG_EN
DEV_ID
REV_ID
Name
RSVD
SGFR
RSVD
DATA
Description
SDRAM Clock: Inverts the clock to the SDRAM interface. Since SSTN and TFT panels do not use
any frame buffer, this bit is used only for DSTN panels.
0 = Use inverted clock.
1 = Use non-inverted clock.
SDRAM or EDO: Selects external frame buffer memory type. Since SSTN and TFT panels do not use
any frame buffer, this bit is used only for DSTN panels. 0 = EDO; 1 = SDRAM.
Reserved: Set to 0.
Dither RAM Access Bit: Allows reads and writes to and from dither RAM.
0 = Disable (Do not allow reads or writes).
1 = Enable (Allow reads and writes).
To perform dither RAM reads and writes, bits 7 and 6 must be set to 1. In addition, Offset 40Ch bits 12
and 0 must be set to 1. If any of these bits are not set to 1, the RAM goes into power-down mode.
Dither RAM Update: This bit works in conjunction with bit 7. If this bit is enabled, it allows the data to
update the RAM.
0 = Disable (do not allow dither RAM access).
1 = Enable (allow dither RAM access).
To perform dither RAM reads and writes, bits 7 and 6 must be set to 1. In addition, Offset 40Ch bits 12
and 0 must be set to 1. If any of these bits are not set to 1, the RAM goes into power-down mode.
Dither RAM Address: This 6-bit field specifies the address to be used for the next access to the
dither RAM. Each access to the data register automatically increments the RAM address register. If
non-sequential access is made to the dither RAM, the address register must be reloaded before each
non-sequential data block.
RAM Data: This 32-bit field contains the read or write data for the RAM access.
Signature Address (Read Only): 24-bit signature data for dither logic or FRM logic.
Frame Count: Represents the frame count, which is an index for the generated signature for that
frame.
Signature Free Run: The value of this bit during the first cycle of a frame determines whether a sig-
nature will be generated for that frame. If this bit is kept high, with signature enabled (bit 0 = 1), the
signature generator captures data continuously across multiple frames. Changing this bit from high-to-
low causes the signature generation process to stop after the current frame.
0 = Do not capture signature during next frame.
1 = Capture signature during next frame.
Signature Enable: Enables/disables signature capture. 0 = Disable; 1 = Enable.
Device ID (Read Only): This 16-bit field contains the data that represents the device ID.
Revision ID (Read Only): This 16-bit field contains the data that represents the revision ID.
Reserved (Read Only)
GPIO7 Pin State (Read Only): Reports the value of pin GPIO7 when it is configured as an input.
GPIO6 Pin State (Read Only): Reports the value of pin GPIO6 when it is configured as an input.
GPIO5 Pin State (Read Only): Reports the value of pin GPIO5 when it is configured as an input.
GPIO4 Pin State (Read Only): Reports the value of pin GPIO4 when it is configured as an input.
GPIO3 Pin State (Read Only): Reports the value of pin GPIO3 when it is configured as an input.
GPIO2 Pin State (Read Only): Reports the value of pin GPIO2 when it is configured as an input.
GPIO1 Pin State (Read Only): Reports the value of pin GPIO1 when it is configured as an input.
GPIO0 Pin State (Read Only): Reports the value of pin GPIO0 when it is configured as an input.
GPIO7 Pin Configuration: Reflects the level of GPIO7. 0 = Low, 1 = High. (Note)
GPIO6 Pin Configuration: Reflects the level of GPIO6. 0 = Low, 1 = High. (Note)
(Continued)
Table 4-2. Configuration Registers (Continued)
Dither RAM Control and Address Register
Device and Revision ID Register (RO)
Panel CRC Signature Register (R/W)
Dither RAM Data Register (R/W)
GPIO Data Register (R/W)
46
Reset Value = 00000000h
Reset Value = 00000000h
Reset Value = xxxxxxxxh
Reset Value = 92110303h
Reset Value = xxxxxx00h
Revision 2.1