CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 23

• Manufacturer Part Number: CS9211-VNG
• Manufacturer: National Semiconductor

Specifications of CS9211-VNG

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Revision 2.1
Functional Description
3.2.3.2
There are two separate pass-through bits to select internal
or external generation of the output timing signals. The
PASS_THRU bit, Offset 404h[30] is global and affects
whether Offset 400h[7:0], Offset 404h[29], and Offset
404h[27:24] control bits will apply or not. The second pass-
through is the HSYNC_SRC bit, Offset 400h[27], and it
determines if the incoming FP_HSYNC pulse will be
passed through unmodified or not. See Table 3-8 on page
24 for descriptions on these bits.
HSYNC
Two groups of bits (Offset 400h[7:5] and Offset 400h[4:0])
control the positions of the leading and trailing edges of the
output HSYNC pulse, also called LP (Latch Pulse), LINE,
or CL1 for some panels. These two groups are effective
only if HSYNC_SRC, Offset 400h[27], is set to 1.
Regardless of the input or output polarity, the two groups of
bits move the leading and trailing edges of the output
HSYNC pulse with respect to the leading edge of the input
HSYNC pulse, as shown in Figure 3-8. Note the difference
between the terms “leading edge” and “rising edge”, and
“trailing edge” and “falling edge”.
Offset 400h[7:5] controls the position of the leading edge of
the output HSYNC pulse with respect to the leading edge
of the input HYSNC pulse. The leading edge of the output
pulse may be delayed with respect to the leading edge of
the input HYSNC pulse in increments of one DOTCLK.
Table 3-6 details the amount of delay in DOTCLK incre-
ments for each setting of Offset 400h[7:5]; note that there
is a skip in the otherwise logical order of increasing delays
from 000 to 001.
HSYNC Leading Edge
400h[7:5]
Offset
000
001
010
011
100
101
110
111
Output Timing Signals
DOTCLK
Delays
No. of
0
2
3
4
5
6
7
8
400h[4:0]
Offset
00000
00001
00010
00011
00100
00101
00110
00111
(Continued)
Table 3-6. HSYNC Edge Position Control
DOTCLK
No Pulse
Delays
No. of
1
2
3
4
5
6
7
400h[4:0]
Offset
01000
01001
01010
01011
01100
01101
01110
01111
23
Offset 400h[4:0] controls the position of the trailing edge of
the output HSYNC pulse with respect to the leading edge
of the input HYSNC pulse. The trailing edge of the output
pulse may be delayed with respect to the leading edge of
the input HYSNC pulse in increments of one DOTCLK.
Table 3-6 details the amount of delay in DOTCLK incre-
ments for each setting of Offset 400h[4:0]; note that a set-
ting of 00000 will result in no output pulse. Note also that
with this scheme it is possible to erroneously program an
output pulse whose trailing edge occurs before the leading
edge! In such a case there will be no output pulse.
The polarity of the HSYNC output pulse may be controlled
by Offset 404h[22], only if Offset 404h[26] = 1.
HSYNC Trailing Edge
DOTCLK
Delays
No. of
Offset 400h[7:5]
10
11
12
13
14
15
8
9
HSYNC
(Pin 97)
HSYNC
(Pin 31)
Output
Leading Edge
Figure 3-8. Control of HSYNC Output
controlled by
Input
Position
400h[4:0]
Offset
10000
10001
10010
10011
10100
10101
10110
10111
Offset 400h[4:0]
Trailing Edge
DOTCLK
controlled by
Delays
No. of
Leading Edge
16
17
18
19
20
21
22
23
Position
400[4:0]
Offset
11000
11001
11010
11011
11100
11101
11110
11111
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DOTCLK
Delays
No. of
24
25
26
27
27
29
30
31