CS9211-VNG National Semiconductor, CS9211-VNG Datasheet - Page 30

• Manufacturer Part Number: CS9211-VNG
• Manufacturer: National Semiconductor

Specifications of CS9211-VNG

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Functional Description
Figure 3-10 shows the order in which pixels will be dithered
down to the next available intensity, as the least significant
bits increase from “0”, for 1-, 2-, 3-, and 4-bit dithering.
The values are given in hexadecimal. The CS9211 also
supports 5-bit dithering but that pattern is not shown.
The patterns shown in Figure 3-10 are stored in the
CS9211’s internal ROM. These patterns will be used when
the dither ROM is selected by Offset 40Ch[12] = 0.
3.2.6.3
Table 3-13 "Dithering Programming Bits" on page 32 indi-
cates the register settings used to control the dithering pro-
cess.
The incoming pixel data goes through the dithering logic.
Dither logic is enabled by writing a “1” to Offset 40Ch[0]. If
Controlling Dithering
F
3
C
F
3
C
3
3
3
3
7
B
4
8
7
B
4
8
1
2
1
2
1
2
1
2
D
E
D
E
1
2
1
2
4-Bit Scheme
3
3
3
3
2-Bit Scheme
(Continued)
A
A
5
9
6
5
9
6
1
2
1
2
1
2
1
2
Figure 3-10. N-Bit Dithering Pattern Schemes
C
C
F
3
F
3
3
3
3
3
B
B
7
4
8
7
4
8
1
2
1
2
1
2
1
2
D
E
D
E
1
2
1
2
3
3
3
3
A
A
5
9
6
5
9
6
1
2
1
2
1
2
1
2
30
the dithering logic is disabled, then only FRM will be pro-
ducing the color intensities. FRM cannot be turned off.
The first step in setting the registers is to decide how to
split the incoming bits per pixel between bits used for FRM
and bits used for dithering. Offset 40Ch[6:4, 3:1] deter-
mines these settings; these two groups of bits must be set
to match each other.
Next, the user must decide whether to use the pre-pro-
grammed (ROM) internal dithering patterns or create new
ones in the dither RAM. If RAM will be used, program Off-
set 40Ch[12] and Offset 424h[7:6] accordingly. If pre-pro-
grammed dither patterns (ROM) will be used, the dither
RAM will go into a reduced power state when it is de-
selected by Offset 40Ch[12] = 0 and Offset 424h[7:6] = 00.
1
7
2
1
7
2
1
1
1
1
5
3
6
4
5
3
6
4
1
1
1
1
2
1
7
2
1
7
1
1
1
1
3-Bit Scheme
1-Bit Scheme
6
4
5
3
6
4
5
3
1
1
1
1
1
7
2
1
7
2
1
1
1
1
5
3
6
4
5
3
6
4
1
1
1
1
2
1
7
2
1
7
1
1
1
1
6
4
5
3
6
4
5
3
1
1
1
1
Revision 2.1