LSISAS1068 LSI, LSISAS1068 Datasheet - Page 105

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

31
0
0
0
0
0
0
0
Register: 0x0C
Test Base Address
Read/Write
The Test Base Address register specifies the base address for Memory
Space [1] accesses.
PCI I/O Space and Memory Space Register Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
0
0
0
0
0
Diagnostic Read/Write Enable
Setting this bit enables access to the
Read/Write Data
registers.
TTL Interrupt
Setting this bit configures PCI INTA/ as a TTL output.
Clearing this bit configures PCI INTA/ as an open-drain
output. Use this bit for test purposes only.
Reset Adapter
Setting this write only bit causes a hard reset within the
LSISAS1068. The bit self-clears after eight PCI clock
periods. After deasserting this bit, the IOP ARM
processor executes from its default reset vector.
DisARM
Setting this bit disables the ARM processor.
Diagnostic Memory Enable
Setting this bit enables diagnostic memory accesses
through PCI Memory Space [1]. Clearing this bit disables
diagnostic memory accesses to PCI Memory Space [1]
and returns 0xFFFF on reads.
Test Base Address
The number of significant bits is determined by the size
of the PCI Memory Space [1] in the NVData image.
Reserved
This field is reserved.
0
0
Test Base Address
0
16 15
0
0
0
and
0
0
Diagnostic Read/Write Address
0
0
0
8
0
7
0
0
Diagnostic
0
0
0
0
[31:10]
0
[9:0]
4-35
0
0
4
3
2
1
0