LSISAS1068 LSI, LSISAS1068 Datasheet - Page 76

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

4-6
PCI Host Register Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Received Target Abort (from Master)
A master device sets this bit when a Target Abort
command terminates its transaction.
Signaled Target Abort
The target device must set this bit when it terminates a
transaction with a target abort command.
DEVSEL/ Timing
These two read only bits encode the timing of DEVSEL/
and indicate the slowest time that a device asserts
DEVSEL/ for any bus command except Configuration
Read and Configuration Write. The LSISAS1068 only
supports medium DEVSEL/ timing. The possible timing
values are:
Data Parity Error Reported
This bit is set per the PCI Local Bus Specification,
Revision 3.0, and PCI-X Addendum to the PCI Local Bus
Specification, Revision 2.0. Refer to bit 0 of the
Command
Reserved
This field is reserved.
66 MHz Capable
The MAD[13] Power-On Sense pin controls this bit.
Allowing the internal pull-down to pull MAD[13] LOW sets
this bit and indicates to the host system that the
LSISAS1068 PCI function is capable of operating at
66 MHz. Pulling MAD[13] HIGH clears this bit and
indicates to the host system that the LSISAS1068 PCI
function is not configured to operate at 66 MHz. Refer to
Section 3.12, “Power-On Sense Pins Description,”
more information.
0b00
0b01
0b10
0b11
register for more information.
Reserved
Medium
Slow
Fast
PCI-X
for
[10:9]
[7:6]
12
11
8
5