TSX5070FN STMicroelectronics, TSX5070FN Datasheet - Page 11

• Manufacturer Part Number: TSX5070FN
• Manufacturer: STMicroelectronics
• Type: PCMr

Specifications of TSX5070FN

• Number Of Channels: 1
• Gain Control: Programmable
• Number Of Adc's: 1
• Number Of Dac's: 1
• Package Type: PLCC
• Operating Supply Voltage (typ): ±5V
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Operating Supply Voltage (max): ±5.25V
• Operating Supply Voltage (min): ±4.75V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Alternatively, the internal time-slot assignment
counters and comparators can be used to access
any time-slot in a frame, using the frame sync inputs
as marker pulses for the beginning of transmit and
receive time-slot 0. In this mode, a frame may con-
sist of up to 64 time-slots of 8 bits each. A time-slot
is assigned by a 2-byte instruction as shown in table
1 and 6. The last 6 bits of the second byte indicate
the selected time-slot from 0-63 using straight bi-
nary notation. A new assignment becomes active
on the second frame following the end of the Chip
Select for the second control byte. The "EN" bit al-
lows the PCM inputs D
propriate, to be enabled or disabled.
Time-Slot Assignment mode requires that the FS
and FS
format shown in figure 6.
PORT SELECTION
On the TS5070 only, an additional capability is
available : 2 Transmit serial PCM ports, D
D
are provided to enable two-way space switching to
be implemented. Port selections for transmit and
receive are made within the appropriate time-slot
Table 7: Byte 2 of Transmit Gain Instructions.
(*) State at power initialization
RECEIVE GAIN INSTRUCTION BYTE 2
The receive gain can be programmed in 0.1 dB
steps by writing to the Receive Gain Register as de-
fined in table 1 and 8. Note the following restriction
on output drive capability :
a) 0 dBm0 levels
driven into a load of
b) 0 dBm0 levels
driven into a load of
c) 0 dBm levels
X
7
0
0
0
1
1
1
1, and 2 receive serial PCM ports, D
R
6
0
0
0
0
1
1
pulses must conform to the delayed timing
5
0
0
0
1
1
1
6.9dBm at VF
Bit Number
4
0
0
0
1
1
1
R
600
8.1dBm at VF
15 k to GND,
7.6dBm at VF
0/1 or outputs D
3
0
0
0
1
1
1
to GND,
R
2
0
0
0
1
1
1
O may be driven
R
R
R
O may be
O may be
1
0
0
1
1
1
1
X
0 and D
0/1 as ap-
X
0 and
0
0
1
0
1
0
1
R
1,
X
assignment instruction using the "PS" bit in the sec-
ond byte.
On the TS5071, only ports D
able, therefore the "PS" bit MUST always be set to
0 for these devices.
Table 6 shows the format for the second byte of
both transmit and receive time-slot and port assign-
ment instructions.
TRANSMIT GAIN INSTRUCTION BYTE 2
The transmit gain can be programmed in 0.1 dB
steps by writing to the Transmit Gain Register as
defined in tables 1 and 7. This corresponds to a
range of 0 dBm0 levels at VF
Vrms and 0.087 Vrms (equivalent to + 6.4 dBm to
– 19.0 dBm in 600 ).
To calculate the binary code for byte 2 of this in-
struction for any desired input 0 dBm0 level in
Vrms, take the nearest integer to the decimal
number given by :
and convert to the binary equivalent. Some exam-
ples are given in table 7.
into a load of
To calculate the binary code for byte 2 of this in-
struction for any desired output 0 dBm0 level in
Vrms, take the nearest integer to the decimal num-
ber given by :
a
n
d convert to the binary equivalent. Some exam-
ples are given in table 8.
In dBm (Into 600 )
No Output
– 18.9
– 19
+6.3
+6.4
0
0dBm0 Test Leve at VF
200 X log
200 X log
300
10
10
to GND.
(V/
(V/
X
6
6
0 and D
In Vrms (approx.)
TS5070 - TS5071
) + 191
) + 174
X
X
I
I between 1.619
0.087
0.088
0.775
1.60
1.62
R
0 are avail-
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