TSX5070FN STMicroelectronics, TSX5070FN Datasheet - Page 20

• Manufacturer Part Number: TSX5070FN
• Manufacturer: STMicroelectronics
• Type: PCMr

Specifications of TSX5070FN

• Number Of Channels: 1
• Gain Control: Programmable
• Number Of Adc's: 1
• Number Of Dac's: 1
• Package Type: PLCC
• Operating Supply Voltage (typ): ±5V
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Operating Supply Voltage (max): ±5.25V
• Operating Supply Voltage (min): ±4.75V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TS5070 - TS5071
Figure 6: Delayed Data Timing (short frame mode)
SERIAL CONTROL PORT TIMING
INTERFACE LATCH TIMING
MASTER RESET PIN
Symbol
Symbol
Symbol
t
f
t
t
t
t
t
t
SSCO
t
t
t
t
t
CCLK
t
t
t
WMR
WCH
WCL
t
t
HCS
HSC
SSC
SDC
HCD
DCD
DSD
DDZ
SLC
HCL
DCL
RC
FC
Frequency of CCLK
Period of CCLK High (measured from V
Period of CCLK Low (measured from V
Rise Time of CCLK (measured from V
Fall Time of CCLK (measured from V
Hold Time, CCLK Low to CS Low (CCLK1)
Hold Time, CCLK Low to CS High (CCLK8)
Setup Time, CS Transition to CCLK Low
Setup Time, CS Transition to CCLK High (to insure CO is not
enabled for single byte)
Setup Time, CI (CI/O) Data in to CCLK low
Hold Time, CCLK Low to CI (CI/O) Invalid
Delay Time, CCLK High to CO (CI/O) Data Out Valid
(load = 100 pF plus 2 LSTTL loads)
Delay Time, CS Low to CO (CI/O) Valid
(applies only if separate CS used for byte 2)
Delay Time, CS or CCLK9 High to CO (CI/O) High Impedance
(applies to earlier of CS high or CCLK9 high)
Setup Time, I
Hold Time, I
Delay Time, CCLK 8 of Byte 2 Low to I
Duration of Master Reset High
L
L
Valid from CCLK 8 of Byte 1 Low. I
Valid to CCLK 8 of Byte 1 Low. I
Parameter
Parameter
Parameter
IH
IL
IL
L
to V
IH
to V
. C
to V
to V
L
IL
IH
= 50 pF. I
)
IL
)
IH
)
)
L
L
as Input
as Input
L
as Output
Min.
Min.
Min.
160
160
100
100
10
70
50
50
50
15
50
1
Typ.
Typ.
Typ.
2.048
Max.
Max.
Max.
200
50
50
80
80
80
MHz
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20/32
s