TSX5070FN STMicroelectronics, TSX5070FN Datasheet - Page 19

• Manufacturer Part Number: TSX5070FN
• Manufacturer: STMicroelectronics
• Type: PCMr

Specifications of TSX5070FN

• Number Of Channels: 1
• Gain Control: Programmable
• Number Of Adc's: 1
• Number Of Dac's: 1
• Package Type: PLCC
• Operating Supply Voltage (typ): ±5V
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Operating Supply Voltage (max): ±5.25V
• Operating Supply Voltage (min): ±4.75V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TIMING SPECIFICATIONS (continued)
PCM INTERFACE TIMING
Figure 5: Non Delayed Data Timing (short frame mode)
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
BCLK
WBH
WBL
t
t
HBF
DBD
DBZ
DBT
DFD
SDB
HBD
SFB
ZBT
RB
FB
Frequency of BCLK (may vary from 64KHz to 4.096MHz in 8KHz
increments, TS5070 only)
Period of BCLK High (measured from V
Period of BCLK Low (measured from V
Rise Time of BCLK (measured from V
Fall Time of BCLK (measured from V
Hold Time, BCLK Low to FS
Setup Time FS
Delay Time, BCLK High to Data Valid (load = 100pF plus 2 LSTTL
loads)
Delay Time from BCLK8 Low to Dx Disabled (if FSx already low);
FSx Low to Dx Disabled (if BCLK8 low);
BCLK9 High to Dx Disabled (if FSx still high)
Delay Time from BCLK and FSx Both High to TSx Low (Load = 100pF
plus 2 LSTTL loads)
Delay Time from BCLK8 low to TSx Disabled (if FSx already low);
FSx Low to TSx Disabled
BCLK9 High to TSx Disabled
Delay Time, FSx High to Data Valid (load = 100pF plus 2 LSTTL
loads, applies if FSx rises later than BCLK rising edge in non-
delayed data mode only)
Setup Time, D
Hold Time, BCLK Low to DR0/1 Invalid
R
X/R
0/1 Valid to BCLK Low
High to BCLK Low
X/R
Parameter
High or Low
IH
IL
IL
to V
IH
to V
to V
to V
IL
IH
(if BCLK8 low);
)
IL
(if FSx still high);
)
IH
)
)
Min.
64
80
80
30
30
15
15
30
20
Typ.
TS5070 - TS5071
Max.
4096
30
30
80
80
60
60
80
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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